Semiconductor packages
AssigneeSamsung Electronics Co., Ltd.
InventorsJinnam Kim, Seokho Kim, Hoonjoo Na, Kwangjin Moon
Life of this patent
Estimating the term…
Abstract
A semiconductor package includes a first structure including a first semiconductor chip, and a second structure on the first structure. The second structure includes a second semiconductor chip, a semiconductor pattern horizontally spaced apart from the second semiconductor chip and on a side surface of the second semiconductor chip, an insulating gap fill pattern between the second semiconductor chip and the semiconductor pattern, and through-electrode structures. At least one of the through-electrode structures penetrates through at least a portion of the second semiconductor chip or penetrates through the semiconductor pattern.
Claims20
A semiconductor package, comprising:
- a first structure comprising a first semiconductor chip comprising a first semiconductor integrated circuit;
- and
- a second structure on the first structure,
- wherein the second structure comprises a second semiconductor chip comprising a second semiconductor integrated circuit, a semiconductor pattern horizontally spaced apart from the second semiconductor chip and on a side surface of the second semiconductor chip, an insulating gap fill pattern between the second semiconductor chip and the semiconductor pattern, and through-electrode structures,
- wherein at least one of the through-electrode structures penetrates through at least a portion of the second semiconductor chip or penetrates through the semiconductor pattern, and wherein the semiconductor pattern is free of a semiconductor integrated circuit at a same height level as the second semiconductor integrated circuit of the second semiconductor chip.
A semiconductor package, comprising:
- a first structure comprising a first semiconductor chip;
- and
- a second structure on the first structure,
- wherein the second structure comprises a bonding structure bonded to the first semiconductor chip, a second semiconductor chip on the bonding structure, a semiconductor pattern on the bonding structure and horizontally spaced apart from the second semiconductor chip, and an insulating gap fill pattern between the second semiconductor chip and the semiconductor pattern,
- wherein the first semiconductor chip comprises a first semiconductor substrate and a first circuit area,
- wherein the second semiconductor chip comprises a second semiconductor substrate and a second circuit area,
- wherein the first circuit area and the second circuit area are between the first semiconductor substrate and the second semiconductor substrate, and
- wherein the semiconductor pattern at least partially surrounds the second semiconductor chip in a plan view.
A semiconductor package, comprising:
- a first semiconductor chip;
- a second semiconductor chip on the first semiconductor chip;
- a semiconductor pattern on the first semiconductor chip and horizontally spaced apart from the second semiconductor chip, the semiconductor pattern at least partially surrounding the second semiconductor chip in a plan view;
- and
- an insulating gap fill pattern between the second semiconductor chip and the semiconductor pattern,
- wherein a distance between the semiconductor pattern and the second semiconductor chip is about 0.5 μm to about 10 μm,
- wherein a thickness of the second semiconductor chip is about 3 μm to about 10 μm,
- wherein a thickness of the first semiconductor chip is greater than the distance between the semiconductor pattern and the second semiconductor chip,
- wherein the thickness of the first semiconductor chip is greater than a thickness of the semiconductor pattern, and
- wherein the thickness of the first semiconductor chip is greater than the thickness of the second semiconductor chip.
Dependencies are inferred from the claim text.