Integrated circuit chip including a passivation nitride layer in contact with a high voltage bonding pad and method of making

An integrated circuit chip, comprising:

• a front end of line (FEOL) structure;
• a back end of line (BEOL) structure over the FEOL structure;
• wherein the BEOL structure includes:
• a bonding pad;
• a passivation layer covering a peripheral region of the bonding pad and including a first opening extending through the passivation layer to reach an upper surface of the bonding pad, said first opening defining a first sidewall of the passivation layer;
• a nitride layer covering an upper surface of the passivation layer, extending along and in contact with said first sidewall of the passivation layer and further including a foot portion extending from the first sidewall within said first opening in contact with the upper surface of the bonding pad;
• and
• an insulator layer covering the nitride layer and including a second opening extending through both the insulator layer and the foot portion of the nitride layer and exposing the upper surface of the bonding pad.