Vertical interconnect elevator based on through silicon vias

A chip package comprising:

• a first integrated-circuit (IC) chip comprising a first semiconductor substrate, a plurality of first transistors at a surface of the first semiconductor substrate and a first interconnection scheme over the surface of the first semiconductor substrate, wherein the first interconnection scheme comprises a first interconnection metal layer over the surface of the first semiconductor substrate, a second interconnection metal layer over the first interconnection metal layer and a first insulating dielectric layer between the first and second interconnection metal layers;
• a second integrated-circuit (IC) chip at a same horizontal level as the first integrated-circuit (IC) chip, wherein the second integrated-circuit (IC) chip comprises a second semiconductor substrate, a plurality of second transistors at a surface of the second semiconductor substrate and a second interconnection scheme over the surface of the second semiconductor substrate, wherein the second interconnection scheme comprises a third interconnection metal layer over the surface of the second semiconductor substrate, a fourth interconnection metal layer over the third interconnection metal layer and a second insulating dielectric layer between the third and fourth interconnection metal layers;
• a first polymer layer at a same horizontal level as the first and second integrated-circuit (C) chips, wherein the first polymer layer comprises a first molding compound and has a portion in a gap between the first and second integrated-circuit (IC) chips;
• a bridge over the first and second integrated-circuit (IC) chips, having a left sidewall vertically over the first integrated-circuit (IC) chip and a right sidewall vertically over the second integrated-circuit (IC) chip, wherein the bridge extends from the left sidewall to the right sidewall across over, in sequence, a right edge of the first integrated-circuit (IC) chip and a left edge of the second integrated-circuit (IC) chip, wherein the bridge is over the portion of the first polymer layer, wherein the bridge comprises a silicon substrate over the first and second integrated-circuit (IC) chips, extending across the right edge of the first integrated-circuit (IC) chip and the left edge of the second integrated-circuit (IC) chip, and a third interconnection scheme under and on the silicon substrate of the bridge, wherein the third interconnection scheme comprises a fifth interconnection metal layer under the silicon substrate of the bridge, wherein the fifth interconnection metal layer couples the first integrated-circuit (IC) chip to the second integrated-circuit (IC) chip;
• a first metal via over the first integrated-circuit (IC) chip and at a same horizontal level as the bridge, extending in a vertical direction;
• a second metal via over the second integrated-circuit (IC) chip and at the same horizontal level as the bridge and first metal via, extending in the vertical direction;
• a second polymer layer over the first polymer layer and first and second integrated-circuit (IC) chips and at the same horizontal level as the bridge and first and second metal vias, wherein the second polymer layer has a first portion between the first metal via and the left sidewall of the bridge and a second portion between the second metal via and the right sidewall of the bridge, wherein the second polymer layer comprises a second molding compound;
• and
• a fourth interconnection scheme over the bridge, second polymer layer and first and second metal vias, wherein the fourth interconnection scheme comprises a sixth interconnection metal layer over the bridge, second polymer layer and first and second metal vias, a seventh interconnection metal layer over the sixth interconnection metal layer and a third insulating dielectric layer between the sixth and seventh interconnection metal layers, wherein the sixth interconnection metal layer couples to the first integrated-circuit (IC) chip through the first metal via and couples to the second integrated-circuit (IC) chip through the second metal via.