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US 11,887,924 B2Granted
Chip scale package
AssigneeCirrus Logic, Inc.
InventorsCraig McAdam, Jonathan Taylor, Douglas Macfarlane, John Kerr, James Munger, John Pavelka, Steven A. Atherton
Life of this patent
Estimating the term…
Abstract
The present disclosure relates to a chip scale package (CSP) comprising: a first set of CSP contact balls or bumps; a second set of CSP contact balls or bumps; and a channel routing region, the channel routing region being devoid of any CSP contact balls or bumps.
Claims11
A chip scale package (CSP) comprising:
- a semiconductor die;
- a first set of CSP contact balls or bumps comprising a discontinuous first ring or loop of CSP contact balls or bumps;
- a second set of CSP contact balls or bumps, wherein the first and second sets of CSP contact balls or bumps are coupled to the semiconductor die and are positioned within a perimeter of the semiconductor die;
- and
- a channel routing region, the channel routing region being devoid of any CSP contact balls or bumps;
- wherein the first and second sets of CSP contact balls or bumps are configured for directly mounting the CSP on, and electrically coupling the CSP to, a substrate of a host device incorporating the CSP, and the CSP is approximately the same size as the semiconductor die;
- and
- wherein the channel routing region is provided, at least in part, by a discontinuity in the first ring or loop.
5 more elements
Dependencies are inferred from the claim text.