Multi-pass plating process with intermediate rinse and dry
AssigneeTexas Instruments Incorporated
InventorsPeter John Holverson, Sudtida Lavangkul
Life of this patent
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Abstract
Methods of forming metal interconnections of an integrated circuit include electroplating two or more metal layers over a metal seed layer, rinsing each of the metal layers with deionized water after the electroplating, and drying each of the metal layers after the rinsing. After forming a last metal layer, the two or more metal layers are annealed thereby forming a final metal layer, resulting in a low defect density of the final metal layer.
Claims18
A method of forming an integrated circuit, comprising:
- electroplating a first metal layer over a semiconductor substrate;
- performing a first rinse process that rinses the first metal layer with water;
- performing a first drying process that dries the first metal layer after the first rinse process;
- electroplating a second metal layer on the first metal layer without annealing the first metal layer;
- performing a second rinse process that rinses the second metal layer with water;
- performing a second drying process that dries the second metal layer after the second rinse process;
- annealing the first and second metal layers after the second drying process, thereby forming a final metal layer;
- and
- forming interconnections from the final metal layer, the interconnections electrically connecting electronic components formed in or over the semiconductor substrate.
A method of forming an integrated circuit, comprising:
- forming a plurality of metal layers over a metal seed layer located on surfaces of an opening in a dielectric layer located over a semiconductor substrate, the forming of each metal layer including:
- electroplating a current metal layer on a previous metal layer without annealing the previous metal layer;
- rinsing the current metal layer with water after the electroplating;
- and
- drying the current metal layer after the rinsing;
- annealing the plurality of metal layers only after electroplating a last one of the plurality of metal layers, the annealing forming a final metal layer;
- and
- forming metal lines from the final metal layer, the metal lines electrically connecting electronic components formed in or over the semiconductor substrate.
A method of fabricating an integrated circuit, the method comprising:
- forming a trench in a dielectric layer;
- depositing a barrier layer over surfaces of the trench;
- forming a metal seed layer over the barrier layer;
- electroplating a first copper layer over the metal seed layer;
- first rinsing the first copper layer with water;
- spin-drying the first copper layer after the first rinsing;
- electroplating a second copper layer over the first copper layer;
- second rinsing the second copper layer with water;
- spin-drying the second copper layer after the second rinsing;
- annealing the first copper layer only after electroplating the second copper layer;
- and
- chemical-mechanical polishing the second copper layer after the annealing, thereby forming copper lines within the dielectric layer.
Dependencies are inferred from the claim text.