Interconnect structures and methods of fabrication

A system comprising:

• a processor comprising:
• a transistor comprising:
• a drain contact coupled to a drain;
• a source contact coupled to a source;
• and
• a gate contact coupled to a gate;
• and
• an IC interconnect structure coupled with the transistor, wherein the IC interconnect structure comprises:
• a first dielectric material layer adjacent to at least a portion of a first interconnect feature;
• a second interconnect feature in contact with at least a portion of the first interconnect feature;
• a second dielectric material layer adjacent to at least a portion of the second interconnect feature;
• a third dielectric material layer between the first and second dielectric material layers, wherein the third dielectric material layer is adjacent to the first interconnect feature and in contact with a portion of the second interconnect feature, and wherein the third dielectric material layer has a greater nitrogen content than at least the first dielectric material layer and wherein the third dielectric material layer comprises carbon;
• and
• a fourth dielectric material layer between the second and third dielectric material layers, wherein the fourth dielectric material layer is adjacent to the second interconnect feature and in contact with a portion of the first interconnect feature, wherein the fourth dielectric material layer has a greater nitrogen content than at least the second dielectric material layer, wherein the fourth dielectric material layer comprises carbon, wherein carbon content within the third dielectric material layer decreases with proximity to the second interconnect feature, and wherein carbon content within the fourth dielectric material layer decreases with proximity to the first interconnect feature;
• and
• a power supply comprising an output coupled to the processor.

A method of fabricating an integrated circuit interconnect structure, the method

• comprising:
• preparing a first substrate, the preparing comprising:
• forming a material layer stack comprising a first dielectric material layer and a second dielectric material layer on the first dielectric material layer, wherein the second
• dielectric material layer comprises more nitrogen than the first dielectric material layer, and further comprises carbon;
• forming a first opening in the material layer stack;
• depositing a first conductive material in the first opening;
• and
• forming a first interconnect feature by planarizing the first conductive material and an upper portion of the second dielectric material layer to form a first interconnect feature;
• preparing a second substrate, the preparing comprising:
• forming a second opening in a third dielectric material layer and an underlying fourth dielectric material layer, wherein the third dielectric material layer comprises more nitrogen than the fourth dielectric material layer, and further comprises carbon;
• depositing a second conductive material in the second opening;
• forming a second interconnect feature by planarizing the second conductive material and an upper portion of the third dielectric material layer;
• reducing the carbon content of an uppermost portion of the second and fourth dielectric materials;
• and
• bonding the first substrate with the second substrate by bringing into contact the first interconnect feature and the second interconnect feature.