Memory device and operating method of the memory device
AssigneeSK hynix Inc.
InventorTae Heui Kwon
Life of this patent
Estimating the term…
Abstract
A memory device includes a memory block and a peripheral circuit. The memory block includes a first word line group of word lines included in the memory block and a second word line group of the word lines included in the memory block. The word lines of the first word line group are different from the word lines of the second word line group. The peripheral circuit provides the first word line group and the second word line group with an equalizing voltage during an equalizing section overlapping an erase voltage discharging section for the memory block to constantly keep voltages of the first word line group and the second word line group to the equalizing voltage.
Claims20
A memory device comprising:
- a memory block including a first word line group of word lines included in the memory block and a second word line group of the word lines included in the memory block, the word lines of the first word line group are different from the word lines of the second word line group;
- and
- a peripheral circuit configured to provide the first word line group and the second word line group with an equalizing voltage during an equalizing section overlapping an erase voltage discharging section for the memory block to constantly keep voltages of the first word line group and the second word line group to the equalizing voltage.
A memory device comprising:
- a memory block including a first word line group of word lines included in the memory block and a second word line group of the word lines included in the memory block, the word lines of the first word line group are different from the word lines of the second word line group;
- and
- a peripheral circuit configured to provide, during an erase operation on the memory block, the first word line group and the second word line group respectively with a first word line voltage and a second word line voltage and then constantly provide an equalizing voltage during an equalizing section.
An operating method of a memory device, the operating method comprising:
- providing, during an erasing section, a first word line group of a memory block with a first word line voltage and a second word line group of the memory block with a second word line voltage, which is higher than the first word line voltage;
- providing, during an equalizing section after the erasing section, the first word line group and the second word line group with an equalizing voltage, which is higher than the second word line voltage;
- and
- discharging, during an erase voltage discharging section included in the equalizing section, an erase voltage during the providing of the equalizing voltage.
Dependencies are inferred from the claim text.