Reconfigurable processing-in-memory logic
OwnerDmitri Yudanovinventor
Life of this patent
Estimating the term…
Abstract
An example system implementing a processing-in-memory pipeline includes: a memory array to store data in a plurality of memory cells electrically coupled to a plurality of wordlines and a plurality of bitlines; a logic array coupled to the memory array, the logic array to implement configurable logic controlling the plurality of memory cells; and a control block coupled to the memory array and the logic array, the control block to control a computational pipeline to perform computations on the data by activating at least one of: one or more bitlines of the plurality of bitlines or one or more wordlines of the plurality of wordlines.
Claims20
A system, comprising:
- a memory array to store data in a plurality of memory cells electrically coupled to a plurality of wordlines and a plurality of bitlines;
- a sense amplifier array coupled to the memory array;
- a logic array integrated with the sense amplifier array, the logic array to implement a configurable logic controlling the plurality of memory cells;
- and
- a control block coupled to the memory array and the logic array, the control block to control a computational pipeline to perform computations on the data by activating at least one of:
- one or more bitlines of the plurality of bitlines or one or more wordlines of the plurality of wordlines,
- wherein the control block is further to:
- pre-charge a selected bitline of the plurality of bitlines;
- and
- evaluate, using the configurable logic implementing multi-level voltage evaluation, a row of memory cells addressed by a selected wordline.
A system, comprising:
- a memory array to store data in a plurality of memory cells electrically coupled to a plurality of wordlines and a plurality of bitlines, the memory array to implement configurable logic controlling the plurality of memory cells;
- a sense amplifier array coupled to the memory array, the sense amplifier array comprises a plurality of sense amplifiers, each sense amplifier configured to receive, from a selected bitline of the plurality of bitlines, a signal encoding content of a memory cell coupled to the selected bitline;
- and
- a control block coupled to the memory array, the control block to control a computational pipeline to perform computations on the data by activating at least one of:
- one or more bitlines of the plurality of bitlines or one or more wordlines of the plurality of wordlines,
- wherein the control block is further to:
- pre-charge a selected bitline of the plurality of bitlines;
- and
- evaluate, using the configurable logic implementing multi-level voltage evaluation, a row of memory cells addressed by a selected wordline.
A method, comprising:
- implementing a configurable logic by storing data in a memory array comprising a plurality of memory cells electrically coupled to a plurality of wordlines and a plurality of bitlines;
- activating one or more bitlines of the plurality of bitlines;
- pre-charging a selected bitline of the one or more bitlines;
- and
- receiving, by a sense amplifier, from the selected bitline, a signal encoding content of a memory cell coupled to the selected bitline;
- and
- evaluating, using the configurable logic implementing multi-level voltage evaluation, a row of memory cells addressed by a selected wordline.
Dependencies are inferred from the claim text.