Shift register unit, driving method, gate driving circuit and display device

A shift register unit, comprising a pull-down node control circuit;

• the pull-down node control circuit being electrically connected to an input terminal, a reset terminal, a first voltage terminal, a second voltage terminal and a pull-down node, respectively, and being configured to, under the control of an input signal provided by the input terminal and a reset signal provided by the reset terminal, control the pull-down node to be electrically conducted to the first voltage terminal or the second voltage terminal, and control to hold a potential of the pull-down node,
• wherein the shift register unit further comprises a setting circuit, a pull-up node potential holding circuit, and N pull-up nodes;
• the setting circuit comprises N setting sub-circuits connected in series with each other, wherein N is an integer greater than or equal to 2;
• the pull-up node potential holding circuit comprises N potential holding sub-circuits;
• a control terminal of a first setting sub-circuit is electrically connected to the input terminal, a first terminal of the first setting sub-circuit is electrically connected to the first voltage terminal, a second terminal of the first setting sub-circuit is electrically connected to a first pull-up node, the first setting sub-circuit is configured to, under the control of the input signal, control the first pull-up node to be electrically conducted to the first voltage terminal;
• a control terminal of an n-th setting sub-circuit is electrically connected to the input terminal, a first terminal of the n-th setting sub-circuit is electrically connected to an (n−1)-th pull-up node, a second terminal of the n-th setting sub-circuit is electrically connected to an n-th pull-up node;
• the n-th setting sub-circuit is configured to, under the control of the input signal, control the (n−1)-th pull-up node to be electrically conducted to the n-th pull-up node;
• n is an integer greater than 1 and less than or equal to N;
• a first potential holding sub-circuit is electrically connected to the first pull-up node, and is configured to hold a potential of the first pull-up node;
• an n-th potential holding sub-circuit is electrically connected to the n-th pull-up node, and is configured to hold a potential of the n-th pull-up node.