US 11,887,682 B2 · Anti-fuse memory cell circuit, array circuit and reading and writing method thereof

Abstract

An anti-fuse memory unit circuit, an array circuit and a reading and writing method are disclosed. The advantages of the device and method include: 1. the anti-fuse memory cell circuit is a pure combinational circuit, compared to time sequence circuit, after a delay of a certain time, this disclosed device closes all paths and stops the logic action of entire circuit, thus lowering the static power consumption to approximately 0; 2. this circuit constituted two positive feedback loops through the design of a switch and a logic calculation module, which enables its readout circuit to read “0” or “1” more reliably; 3. this circuit can eliminate a complicated timing sequence control part, even output the anti-fuse codes directly without latching the readout circuit output OUTA/OUTB; 4. this circuit layout is flexible.

Claims15

Dependent claims

An anti-fuse memory cell circuit, comprising:

an anti-fuse device;
a switch module, coupled to the anti-fuse device;
a selection module, coupled to the switch module;
and
a control module, respectively coupled to the anti-fuse device and the switch module;
wherein, the control module is configured to switch an on-off mode of the switch module according to a breakdown state of the anti-fuse device;
wherein the anti-fuse device has a first end and a second end,
wherein the switch module includes a first switch unit and a second switch unit, wherein each of the first switch unit and the second switch unit has a first terminal, a second terminal and a control terminal, wherein the control terminal is coupled to the control module;
and
wherein the second terminals of the first and the second switch units are each coupled to the selection module, wherein the first terminal of the first switch unit is coupled to the first end of the anti-fuse device, and wherein the first terminal of the second switch unit is coupled to the second end of the anti-fuse device.

7 more elements

An anti-fuse memory array circuit, comprising:

at least one control module;
a plurality of anti-fuse memory cell circuits, wherein each of the plurality of anti-fuse memory cell circuits comprises:
an anti-fuse device;
a switch module, coupled to the anti-fuse device;
a selection module, coupled to the switch module;
and
a control module coupled respectively to the anti-fuse device and the switch module of each of the plurality of anti-fuse memory cell circuits, wherein the control module is configured to switch the on-off mode of the switch module according to the breakdown state of the anti-fuse device;
wherein the control module is a master control module, which is respectively coupled to the anti-fuse device of each of the plurality of anti-fuse memory cell circuits and the switch module;
wherein the master control module comprises a control unit, wherein the control unit has an input terminal and an output terminal, wherein the input terminal of the control unit is respectively coupled to the first end of the anti-fuse device of each of the plurality of the anti-fuse memory cell circuits, a write enable signal, a read enable signal, and a read enable delay signal of each of the plurality of anti-fuse memory cell circuits;
and
wherein the output terminal of the control unit is respectively coupled to the switch module of each of the plurality of anti-fuse memory cell circuits.

8 more elements

A method for reading and writing an anti-fuse memory cell circuit, wherein the anti-fuse memory cell circuit comprises:

an anti-fuse device;
a switch module, coupled to the anti-fuse device;
a selection module, coupled to the switch module;
and
a control module, respectively coupled to the anti-fuse device and the switch module;
wherein, the control module is configured to switch an on-off mode of the switch module according to a breakdown state of the anti-fuse device,
wherein the method comprises:
during programming, the control module controls the switch module to be in a first state to perform a write operation on the anti-fuse device;
in standby time, the control module controls the switch module to be in a second state to reduce the power consumption of the anti-fuse device;
and
during normal operation, the control module controls the switch module to be in a third state to perform a read operation on the anti-fuse device.

8 more elements

Dependencies are inferred from the claim text.

Anti-fuse memory cell circuit, array circuit and reading and writing method thereof

Life of this patent

Anti-fuse memory cell circuit, array circuit and reading and writing method thereof

Life of this patent

Abstract

Claims15