Reducing program verifies for multi-level NAND cells

A non-transitory machine-readable medium that stores instructions that, when executed by a system, cause the system to perform operations comprising:

• applying, at a first time, a single-valued first programming voltage to a first group of memory cells of a multi-level cell (MLC) memory array, each MLC of the MLC memory array being programmable to a plurality of levels including a first level and a second level;
• performing a first verify operation to determine a first programming effectiveness metric comprising a first amount of the first group of memory cells that were successfully programmed to the first level in response to the first programming voltage at the first time;
• and
• based on the first programming effectiveness metric and a predetermined threshold, determining whether to perform a second verify operation to determine a second programming effectiveness metric comprising a second amount of the first group of memory cells that were successfully programmed to the second level by the first programming voltage at the first time.

A method comprising:

• applying, at a first time, a single-valued first programming voltage to a first group of memory cells of a multi-level cell (MLC) memory array, each MLC of the MLC memory array being programmable to a plurality of levels including a first level and a second level;
• performing a first verify operation to determine a first programming effectiveness metric comprising a first amount of the first group of memory cells that were successfully programmed to the first level in response to the first programming voltage at the first time;
• and
• based on the first programming effectiveness metric and a predetermined threshold, determining whether to perform a second verify operation to determine a second programming effectiveness metric comprising a second amount of the first group of memory cells that were successfully programmed to the second level by the first programming voltage at the first time.