Quick pass write programming techniques in a memory device

A memory device, comprising:

• an array of memory cells arranged in a plurality of word lines;
• a controller configured to program the memory cells of a selected word line of the plurality of word lines in a plurality of program-verify iterations, during a verify portion at least one of the program-verify iterations, the controller being further configured to:
• determine a threshold voltage of at least one memory cell of the selected word line relative to a first verify low voltage VL1, a second verify low voltage VL2, and a verify high voltage VH associated with a data state being programmed;
• and
• to determine the threshold voltage of the at least one memory cell, the controller is configured to maintain a count of program-verify iterations since the at least one memory cell passed a verify high voltage of a previously programmed data state or is configured to discharge a sense node through a channel including the at least one memory cell and compare a discharge time to predetermined sense times associated with the first and second verify low voltages and with the verify high voltage.

A method of programming a memory device, comprising the steps of:

• preparing a memory device that includes an array of memory cells arranged in a plurality of word lines;
• programming the memory cells of a selected word line of the plurality of word lines in a plurality of program-verify iterations;
• during a verify portion of at least one program-verify iteration of the plurality of program-verify iterations:
• charging a sense node SEN to a charged voltage V_charged;
• concurrently discharging the sense node SEN from the charged voltage V_charged to a sense voltage V_sense through a first set of channels coupled with at least one memory cell that is being programmed to a programmed data state N while a first biasing voltage is applied to at least one bit line coupled with the first set of channels and discharging the sense node SEN through a second set of channels coupled with at least one memory cell that is being programmed to a next programmed data state N+1 while a second biasing voltage that is different than the first biasing voltage is applied to at least one bit line coupled with the second set of channels;
• comparing a discharge time of the sense node SEN from V_charged to V_sense through the first set of channels to a first predetermined sense time T_Sense_VH_N to determine if a threshold voltage of the at least one memory cell being programmed to the data state N has passed a verify high voltage VH of the data state N;
• and
• comparing a discharge time of the sense node SEN from V_charged to V_sense through the second set of channels to a second predetermined sense time T_Sense_VL_N+1 to determine if a threshold voltage of the at least one memory cell being programmed to the data state N+1 has passed a verify low voltage VL of data state N+1.