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US 11,887,675 B2Granted
Random telegraph signal noise reduction scheme for semiconductor memories
OwnerToru Tanzawainventor
Life of this patent
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Abstract
Embodiments are provided that include a memory device having a memory array including a plurality of access lines and data lines. The memory device further includes a circuit coupled to the plurality of access lines and configured to provide consecutive pulses to a selected one of the plurality of access lines. Each pulse of the consecutive pulses includes a first voltage and a second voltage. The first voltage is greater in magnitude than the second voltage, and the first voltage is applied for a shorter duration than the second voltage.
Claims20
A flash memory device comprising:
- a floating gate memory array comprising a plurality of memory cells configured to store respective data values;
- regulating circuitry configured to provide a pulsed wordline signal to a wordline of a memory cell of the plurality of memory cells during a read operation of the memory cell, wherein the pulsed wordline signal varies between a high voltage state and a low voltage state, such that electrons that trap during the high voltage state detrap during the low voltage state;
- and
- sense circuitry configured to integrate a current of a bitline of the memory cell during the read operation and determine a data value of the memory cell based on integration of the current.
1 more element
A computing system comprising:
- flash memory configured to store executable instructions via a floating gate memory array, wherein the flash memory comprises:
- the floating gate memory array comprising a plurality of memory cells;
- regulating circuitry configured to provide a pulsed wordline signal to a wordline of a memory cell of the plurality of memory cells during a read operation of the memory cell, wherein the pulsed wordline signal varies between a high voltage state and a low voltage state such that electrons that trap during the high voltage state detrap during the low voltage state;
- and
- sense circuitry configured to determine a data value of the memory cell based on a bitline response of the memory cell;
- one or more processors communicatively coupled to the flash memory via a data bus and configured to retrieve and execute the executable instructions to perform operations of the computing system;
- and
- a power supply configured to supply power to the flash memory and the one or more processors.
5 more elements
A memory device comprising:
- a floating gate memory array comprising a plurality of memory cells configured to store respective data values;
- an address decoder configured to direct access to a memory cell of the plurality of memory cells for a read operation or a verify operation in response to address information corresponding to the memory cell;
- regulating circuitry configured to provide a time varying wordline signal to a wordline of the memory cell during a discharge period of the read operation of the memory cell or the discharge period of the verify operation of the memory cell, wherein the time varying wordline signal comprises a plurality of pulses, wherein each pulse of the plurality of pulses changes a voltage of the time varying wordline signal from a first voltage state to a second voltage state and returns the voltage to the first voltage state;
- and
- sense circuitry configured to integrate a current response of a bitline of the memory cell during the discharge period and determine a data value of the memory cell based on integration of the current response.
2 more elements
Dependencies are inferred from the claim text.