Utilizing data pattern effect to control read clock timing and bit line kick for read time reduction

A controller in communication with a memory apparatus including memory cells each connected to one of a plurality of word lines and disposed in strings coupled to one of a plurality of bit lines and configured to retain a threshold voltage corresponding to one of a plurality of data states, the controller configured to:

• instruct the memory apparatus to read each of the memory cells in a read operation;
• and
• for each one of the memory cells, instruct the memory apparatus to offset at least one of a bit line settling time and a kick voltage applied to the one of the plurality of bit lines coupled to the one of the memory cells during the read operation based on a probability of at least one neighboring one of the plurality of bit lines being coupled to the memory cells retaining the threshold voltage corresponding to a different one of the plurality of data states than the one of the memory cells.

A method of operating a memory apparatus including memory cells each connected to one of a plurality of word lines and disposed in strings coupled to one of a plurality of bit lines and configured to retain a threshold voltage corresponding to one of a plurality of data states, the method comprising the steps of:

• reading each of the memory cells in a read operation;
• and
• for each one of the memory cells, offsetting at least one of a bit line settling time and a kick voltage applied to the one of the plurality of bit lines coupled to the one of the memory cells during the read operation based on a probability of at least one neighboring one of the plurality of bit lines being coupled to the memory cells retaining the threshold voltage corresponding to a different one of the plurality of data states than the one of the memory cells.