Nonvolatile memory device having a dummy bit line driver and operation method thereof

A nonvolatile memory device comprising:

• a peripheral circuit formed on a semiconductor substrate;
• a memory cell array formed on the peripheral circuit and including a plurality of cell strings;
• and
• a metal layer formed on the memory cell array, wherein:
• the metal layer includes:
• a plurality of bit lines connected with the plurality of cell strings;
• a common source line connected with the plurality of cell strings;
• and
• at least one dummy bit line provided between the plurality of bit lines and the common source line, and
• the peripheral circuit includes:
• a control logic circuit configured to generate at least one dummy bit line driving signal in response to a command from an external device;
• and
• a dummy bit line driver configured to selectively provide a first voltage to the at least one dummy bit line in response to the at least one dummy bit line driving signal, wherein the dummy bit line driver includes:
• a first switch connected between the at least one dummy bit line and a first terminal receiving the first voltage and configured to operate in response to a first dummy bit line driving signal of the at least one dummy bit line driving signal;
• and
• a second switch connected between the at least one dummy bit line and the common source line and configured to operate in response to a second dummy bit line driving signal of the at least one dummy bit line driving signal.

An operation method of a nonvolatile memory device, the method comprising:

• receiving a read command from an external device;
• in response to the read command:
• applying, while a precharge operation is performed on a plurality of bit lines, a precharge voltage to at least one dummy bit line present between the plurality of bit lines and a common source line,
• providing a ground voltage, differing from the precharge voltage, to the at least one dummy bit line while a sensing operation is performed on the plurality of bit lines, and
• performing a read operation;
• receiving an erase command from the external device;
• in response to the erase command, floating the at least one dummy bit line, electrically connecting the at least one dummy bit line and the common source line, or applying an erase voltage to the at least one dummy bit line;
• and
• performing an erase operation in response to the erase command.