US 11,887,670 B2 · Controlling bit line pre-charge voltage separately for multi-level memory cells and single-level memory cells to reduce peak current consumption

Abstract

Apparatuses and techniques are described for controlling a bit line pre-charge voltage in a program operation based on a number of bits per cell, with a goal to reduce peak current consumption. In one aspect, the ramp up of a bit line voltage to an inhibit level is optimized according to the number of bits per cell. The ramp up can involve increasing the bit line voltage from an initial level to a target voltage at a regulated rate, then increasing the bit line voltage from the target voltage to a final voltage at an unregulated rate. In one approach, the regulated ramp rate is less for single-level cell programming compared to multi-level cell programming. The target voltage can also be optimized based on the number of bis per cell.

Claims20

Dependent claims

An apparatus, comprising;

a first voltage source configured to output a program-inhibit voltage signal to unselected bit lines among a plurality of bit lines during a program operation, the plurality of bit lines are connected to respective NAND strings in a set of NAND strings, and the NAND strings comprise memory cells;
and
a control circuit configured to connect to the first voltage source, the control circuit is configured to:
control a ramp up of the program-inhibit voltage signal based on a number of bits per memory cell to program into selected memory cells of the respective NAND strings including ramping up at a first rate when programming a first number of bits per memory cell and ramping up at a second rate when programming a second number of bits per memory cell, the first number is less than the second number and the first rate is less than the second rate.

1 more element

An apparatus, comprising:

a set of memory cells connected to a selected word line, each memory cell is arranged in a respective NAND string of a set of NAND strings;
a set of bit lines, each bit line is connected to a respective NAND string in the set of NAND strings;
and
a first voltage source configured to apply a program-inhibit voltage signal to selected bit lines in the set of bit lines, the first voltage source is configured to increase the program-inhibit voltage signal from an initial voltage to a program-inhibit voltage and, when a program pulse is applied to the selected word line in a program operation, to maintain the program-inhibit voltage signal at the program-inhibit voltage, the increasing of the program-inhibit voltage signal is a function of a number of bits per memory cell to be stored in the set of memory cells in the program operation such that the program-inhibit voltage signal is increased at a first rate when programming a single bit per memory cell and increased at a second rate when programming multiple bits per memory cell, the first rate is less than the second rate.

1 more element

Dependencies are inferred from the claim text.

Controlling bit line pre-charge voltage separately for multi-level memory cells and single-level memory cells to reduce peak current consumption

Life of this patent

Controlling bit line pre-charge voltage separately for multi-level memory cells and single-level memory cells to reduce peak current consumption

Life of this patent

Abstract

Claims20