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US 11,887,656 B2Granted
Memory for improving efficiency of error correction
AssigneeSK hynix Inc.
InventorsMin Soo Yoo, Eun Hyup Doh
Life of this patent
Estimating the term…
Abstract
A memory includes: a plurality of row lines; a plurality of column lines; and a plurality of memory cells each of which is coupled to one row line among the row lines and one column line among the column lines, wherein memory cells corresponding to a row line which is selected based on a row address among the row lines are simultaneously activated, and data are read from memory cells corresponding to column lines which are selected based on a column address among the activated memory cells, and the selected column lines are not adjacent to each other.
Claims6
A memory, comprising:
- a first cell array including a plurality of row lines, a plurality of first column lines, and a plurality of first memory cells, each of which is coupled to one row line among the row lines and one column line among the first column lines;
- a second cell array arranged adjacent to the first cell array, sharing the row lines with the first cell array, and including a plurality of second column lines and a plurality of second memory cells, each of which is coupled to one row line among the row lines and one column line among the second column lines;
- a third cell array arranged adjacent to the second cell array, sharing the row lines with the second cell array, and including a plurality of third column lines and a plurality of third memory cells, each of which is coupled to one row line among the row lines and one column line among the third column lines;
- a first even bit line sense amplifier array positioned on one side of the first cell array and suitable for amplifying data of the first memory cells corresponding to a selected row line and even first column lines among the first column lines;
- a first odd bit line sense amplifier array positioned on another side of the first cell array and suitable for amplifying data of the first memory cells corresponding to the selected row line and odd first column lines among the first column lines;
- a second even bit line sense amplifier array positioned on one side of the second cell array and suitable for amplifying data of the second memory cells corresponding to the selected row line and even second column lines among the second column lines;
- a second odd bit line sense amplifier array positioned on another side of the second cell array and suitable for amplifying data of the second memory cells corresponding to the selected row line and odd second column lines among the second column lines;
- a third even bit line sense amplifier array positioned on one side of the third cell array and suitable for amplifying data of the third memory cells corresponding to the selected row line and even third column lines among the third column lines;
- and
- a third odd bit line sense amplifier array positioned on another side of the third cell array and suitable for amplifying data of the third memory cells corresponding to the selected row line and odd third column lines among the third column lines,
- wherein during a read operation, each of the first odd bit line sense amplifier array and the third even bit line sense amplifier array is suitable for outputting data therefrom, and
- wherein during the read operation, each of the first even bit line sense amplifier array, the second even bit line sense amplifier array, the second odd bit line sense amplifier array, and the third odd bit line sense amplifier array is suitable for preventing output of data therefrom.
9 more elements
A memory, comprising:
- a first cell array including a plurality of row lines, a plurality of first column lines, and a plurality of first memory cells, each of which is coupled to one row line among the row lines and one column line among the first column lines;
- a second cell array arranged adjacent to the first cell array, sharing the row lines with the first cell array, and including a plurality of second column lines and a plurality of second memory cells, each of which is coupled to one row line among the row lines and one column line among the second column lines;
- a third cell array arranged adjacent to the second cell array, sharing the row lines with the second cell array, and including a plurality of third column lines and a plurality of third memory cells, each of which is coupled to one row line among the row lines and one column line among the third column lines;
- a first even bit line sense amplifier array positioned on one side of the first cell array and suitable for amplifying data of the first memory cells corresponding to a selected row line and even first column lines among the first column lines;
- a first odd bit line sense amplifier array positioned on another side of the first cell array and suitable for amplifying data of the first memory cells corresponding to the selected row line and odd first column lines among the first column lines;
- a second even bit line sense amplifier array positioned on one side of the second cell array and suitable for amplifying data of the second memory cells corresponding to the selected row line and even second column lines among the second column lines;
- a second odd bit line sense amplifier array positioned on another side of the second cell array and suitable for amplifying data of the second memory cells corresponding to the selected row line and odd second column lines among the second column lines;
- a third even bit line sense amplifier array positioned on one side of the third cell array and suitable for amplifying data of the third memory cells corresponding to the selected row line and even third column lines among the third column lines;
- and
- a third odd bit line sense amplifier array positioned on another side of the third cell array and suitable for amplifying data of the third memory cells corresponding to the selected row line and odd third column lines among the third column lines,
- wherein during a read operation, each of the first even bit line sense amplifier array and the third odd bit line sense amplifier array is suitable for outputting data therefrom, and
- wherein during the read operation, each of the first odd bit line sense amplifier array, the second even bit line sense amplifier array, the second odd bit line sense amplifier array, and the third even bit line sense amplifier array is suitable for preventing output of data therefrom.
9 more elements
A memory, comprising:
- a first cell array including a plurality of row lines, a plurality of first column lines, and a plurality of first memory cells, each of which is coupled to one row line among the row lines and one column line among the first column lines;
- a second cell array arranged adjacent to the first cell array, sharing the row lines with the first cell array, and including a plurality of second column lines and a plurality of second memory cells, each of which is coupled to one row line among the row lines and one column line among the second column lines;
- a third cell array arranged adjacent to the second cell array, sharing the row lines with the second cell array, and including a plurality of third column lines and a plurality of third memory cells, each of which is coupled to one row line among the row lines and one column line among the third column lines;
- a first even bit line sense amplifier array positioned on one side of the first cell array and suitable for amplifying data of the first memory cells corresponding to a selected row line and even first column lines among the first column lines;
- a first odd bit line sense amplifier array positioned on another side of the first cell array and suitable for amplifying data of the first memory cells corresponding to the selected row line and odd first column lines among the first column lines;
- a second even bit line sense amplifier array positioned on one side of the second cell array and suitable for amplifying data of the second memory cells corresponding to the selected row line and even second column lines among the second column lines;
- a second odd bit line sense amplifier array positioned on another side of the second cell array and suitable for amplifying data of the second memory cells corresponding to the selected row line and odd second column lines among the second column lines;
- a third even bit line sense amplifier array positioned on one side of the third cell array and suitable for amplifying data of the third memory cells corresponding to the selected row line and even third column lines among the third column lines;
- and
- a third odd bit line sense amplifier array positioned on another side of the third cell array and suitable for amplifying data of the third memory cells corresponding to the selected row line and odd third column lines among the third column lines,
- wherein the first even bit line sense amplifier array, the first odd bit line sense amplifier array, the second even bit line sense amplifier array, the second odd bit line sense amplifier array, the third even bit line sense amplifier array, and the third odd bit line sense amplifier array are further suitable for performing respective data amplification operations simultaneously.
8 more elements
Dependencies are inferred from the claim text.