Vertical memory device
AssigneeSK hynix Inc.
InventorsSeung-Hwan Kim, Su-Ock Chung, Seon-Yong Cha
Life of this patent
Estimating the term…
Abstract
A memory device includes: a first memory cell mat that includes first multi-layer level sub word lines positioned over a substrate; a second memory cell mat that is laterally spaced apart from the first memory cell mat and includes second multi-layer level sub word lines; a first sub word line driver circuit that is positioned underneath the first memory cell mat; and a second sub word line driver circuit that is positioned underneath the second memory cell mat, wherein the first sub word line driver circuit is positioned underneath ends of the first multi-layer level sub word lines, and the second sub word line driver circuit is positioned underneath ends of the second multi-layer level sub word lines.
Claims11
A memory device, comprising:
- a peripheral circuit portion including a sub word line driver circuit;
- a bit line oriented vertically over the peripheral circuit portion;
- a capacitor positioned over the peripheral circuit portion;
- and
- an active layer oriented laterally between the bit line and the capacitor;
- and
- a word line extending along a direction intersecting the active layer,
- wherein the sub word line driver circuit is positioned underneath the end of the word line.
Dependencies are inferred from the claim text.