Semiconductor memory device managing flexible refresh skip area
AssigneeSamsung Electronics Co., Ltd.
InventorsUksong Kang, Hoiju Chung
Life of this patent
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Abstract
A semiconductor memory device having a flexible refresh skip area includes a memory cell array including a plurality of rows to store data, a row decoder connected to the memory cell array, a refresh area storage unit to store a beginning address and an end address of a memory area that is to be refreshed in which the memory area that is to be refreshed does not include a refresh skip area having a size is selectively and/or adaptively changed, and a refresh control circuit connected to the row decoder and the refresh area storage unit. The refresh control circuit controls a refresh operation for the area that is to be refreshed and not for the refresh skip area.
Claims20
A semiconductor memory device, comprising:
- a memory cell array including a plurality of memory banks, each of the memory banks including memory cells arranged in a plurality of rows;
- a row decoder connected to the memory cell array;
- a refresh area storage unit configured to store refresh information which classifies the plurality of rows into one of refresh area and refresh skip area, the refresh area being a first group of rows among the plurality of rows in which memory cells connected to the first group of rows to be refreshed and the memory skip area being a second group of rows among the plurality of rows in which memory cells connected to the second group of rows not to be refreshed;
- and
- a refresh control circuit connected to the row decoder, and configured to control a refresh operation for each row of the refresh area to be refreshed and control the refresh operation for each row of the refresh skip area not to be refreshed,
- wherein at least one memory bank among the plurality of memory banks includes both the refresh area and the refresh skip area.
A semiconductor memory device, comprising:
- a memory cell array including a plurality of memory banks, each of the memory banks including memory cells arranged in a plurality of rows;
- a row decoder connected to the memory cell array;
- a refresh area storage unit configured to store refresh information which classifies each of the plurality of rows into one of a first group of rows and a second group of rows respectively;
- and
- a refresh control circuit connected to the row decoder, and configured to control a refresh operation for rows of the first group and for rows of the second group differently,
- wherein at least one memory bank among the plurality of memory banks includes both the first group of rows and the second group of rows.
Dependencies are inferred from the claim text.