Staggering refresh address counters of a number of memory devices, and related methods, devices, and systems
OwnerChristopher G. Wieduwilt, James S. Rehmeyerinventors
Life of this patent
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Abstract
Methods of operating a number of memory devices are disclosed. A method may include receiving, at each of a number of memory devices, a refresh command. The method may also include refreshing, at each of the number of memory devices and in response to the refresh command, a number of memory cells based on a count of an associated refresh address counter, wherein a count of a refresh address counter of at least one memory device of the number of memory devices is offset from a count of a refresh address counter of at least one other memory device of the number of memory devices. Related systems and memory modules are also described.
Claims20
A method, comprising:
- receiving, at each of a number of memory devices, a refresh command;
- and
- refreshing, at each of the number of memory devices substantially simultaneously and in response to the refresh command, a number of memory cells based on a count of an associated refresh address counter, a count of a refresh address counter of at least one memory device of the number of memory devices being offset from a count of a refresh address counter of at least one other memory device of the number of memory devices, wherein a difference between the count of the refresh address counter of the at least one memory device and the count of the refresh address counter of the at least one other memory device is at least partially based on a value of the number of memory devices.
A method, comprising:
- receiving, at a first memory device and a second memory device of a number of memory devices, a refresh command;
- refreshing, at the first memory device and in response to the refresh command, a first number of memory cells based on a first count value of a first refresh address counter of the first memory device;
- and
- refreshing, at the second memory device and in response to the refresh command, a second number of memory cells of the second memory device based on a second count value of a second refresh address counter of the second memory device, wherein the second count value is different from the first count value, wherein a difference between the first count value and the second count value is at least partially based on a value of the number of memory devices, wherein the first number of memory cells and the second number of memory cells are refreshed substantially simultaneously.
A memory module, comprising:
- a number of memory devices, wherein each memory device of the number of memory devices includes:
- a counter having an index, wherein at least one memory device of the number of memory devices includes an index that is different from an index of at least one other memory device of the number of memory devices, wherein a difference between the index of the at least one memory device and the index of the at least one other memory device is at least partially based on a value of the number of memory devices;
- and
- a controller configured to refresh, based on the index of the counter, a number of memory cells;
- wherein the at least one memory device and the at least one other memory device are configured to refresh its associated number of memory cells substantially simultaneously.
A system comprising:
- at least one processor device;
- and
- a number of memory devices operably coupled to the at least one processor device, wherein at least one memory device of the number of memory devices comprises a refresh address counter having a count value offset from a count value of a refresh address counter of at least one other memory device of the number of memory devices, wherein a difference between the count value of the at least one memory device and the count value of the at least one other memory device is at least partially based on a value of the number of memory devices, wherein a number of memory cells of the at least one memory device and a number of memory cells of the at least one other memory device are to be refreshed substantially simultaneously.
Dependencies are inferred from the claim text.