Semiconductor memory devices

A semiconductor memory device, comprising:

• a semiconductor substrate;
• a plurality of memory cell structures each comprising a cell source layer, a channel layer, and a drain layer sequentially stacked from the semiconductor substrate in a vertical direction, and each having a vertical pillar shape extending in the vertical direction;
• a plurality of word line structures being apart from each other in the vertical direction and surrounding the plurality of memory cell structures;
• a plurality of memory cell dielectric layers each interposed between the channel layer of a corresponding one of the plurality of memory cell structures and a corresponding one of the plurality of word line structures;
• and
• a plurality of bit lines each electrically connected to the drain layer of each of the plurality of memory cell structures, respectively, extending in a first horizontal direction on the plurality of word line structures, and having a certain distance from each other in a second horizontal direction orthogonal to the first horizontal direction,
• wherein the drain layer is doped with impurities of a first conductivity type,
• the cell source layer is doped with impurities of a second conductivity type different from the first conductivity type,
• each of the plurality of memory cell dielectric layers comprises:
• a gate insulating layer covering the plurality of word line structures;
• and
• a charge trap layer arranged between the gate insulating layer and the channel layer, and
• each of the plurality of memory cell structures comprises a volatile memory device having a thyristor structure.

A semiconductor memory device, comprising:

• a semiconductor substrate;
• an etch stop layer arranged on the semiconductor substrate, the etch stop layer including an oxynitride;
• a common source semiconductor layer doped with impurities of a first conductivity type and arranged on the semiconductor substrate;
• a plurality of insulating layers and a plurality of word line structures alternately stacked on the common source semiconductor layer;
• a memory cell dielectric layer comprising a gate insulating layer and a charge trap layer sequentially covering an internal sidewall of each of a plurality of channel holes, wherein the plurality of channel holes penetrate the plurality of insulating layers, the plurality of word line structures, and the etch stop layer in a vertical direction, and extend into the semiconductor substrate;
• a plurality of memory cell structures each comprising:
• a filling semiconductor layer arranged on a barrier insulating layer, the filling semiconductor layer located apart from the memory cell dielectric layer and filling some of a lower portion of each of the plurality of channel holes;
• a channel layer arranged on the memory cell dielectric layer, being apart from the filling semiconductor layer with the common source semiconductor layer arranged therebetween, filling a first region of an upper portion of each of the plurality of channel holes, and comprising a material identical to that of the filling semiconductor layer;
• and
• a drain layer covering an upper surface of the channel layer, filling a second region of the upper portion of each of the plurality of channel holes, and doped with impurities of a second conductivity type different from the first conductivity type;
• and
• a plurality of bit lines each electrically connected to the drain layer of each of the plurality of memory cell structures, respectively, extending on the plurality of memory cell structures in a first horizontal direction, and having a certain distance from each other in a second horizontal direction orthogonal to the first horizontal direction.