Pixel drive circuit, display panel, and display device

A display panel, comprising:

• a plurality of pixels, each pixel comprising a plurality of sub-pixel elements;
• and
• a plurality of pixel drive circuits, wherein the plurality of pixel drive circuits are coupled to the plurality of sub-pixel elements in a one-to-one correspondence, and each pixel drive circuit comprises:
• a drive compensation circuitry, comprising a storage capacitor and a drive transistor, wherein an input end of the drive transistor is coupled to a drive-voltage terminal, and an output end of the drive transistor is coupled to one of the plurality of sub-pixel elements;
• a data-writing circuitry, wherein an output end of the data-writing circuitry is coupled to a control end of the drive transistor, to write a data voltage to the control end of the drive transistor in a writing phase;
• and
• a flip-elimination circuitry, wherein the flip-elimination circuitry is configured to write a reference voltage to the control end of the drive transistor through an independent circuit line in a compensation phase, to eliminate a voltage flip formed due to a switching between the data voltage and the reference voltage in the writing phase of the data voltage,
• wherein the flip-elimination circuitry comprises a flip-elimination transistor, the flip-elimination transistor is a four-terminal device, wherein a control end of the flip-elimination transistor is coupled to a third gate-control-signal line, an input end of the flip-elimination transistor is coupled to the control end of the drive transistor, an output end of the flip-elimination transistor is coupled to a reference-voltage line, and a bottom gate of the flip-elimination transistor is coupled to a direct-current signal line.

A display device, comprising:

• a display panel, comprising:
• a plurality of pixels, each pixel comprising a plurality of sub-pixel elements;
• and
• a plurality of pixel drive circuits, wherein the plurality of pixel drive circuits are coupled to the plurality of sub-pixel elements in a one-to-one correspondence, and each pixel drive circuit comprises:
• a drive compensation circuitry, comprising a storage capacitor and a drive transistor, wherein an input end of the drive transistor is coupled to a drive-voltage terminal, and an output end of the drive transistor is coupled to one of the plurality of sub-pixel elements;
• a data-writing circuitry, wherein an output end of the data-writing circuitry is coupled to a control end of the drive transistor, to write a data voltage to the control end of the drive transistor in a writing phase;
• and
• a flip-elimination circuitry, wherein the flip-elimination circuitry is configured to write a reference voltage to the control end of the drive transistor through an independent circuit line in a compensation phase, to eliminate a voltage flip formed due to a switching between the data voltage and the reference voltage in the writing phase of the data voltage,
• wherein the flip-elimination circuitry comprises a flip-elimination transistor, the flip-elimination transistor is a four-terminal device, wherein a control end of the flip-elimination transistor is coupled to a third gate-control-signal line, an input end of the flip-elimination transistor is coupled to the control end of the drive transistor, an output end of the flip-elimination transistor is coupled to a reference-voltage line, and a bottom gate of the flip-elimination transistor is coupled to a direct-current signal line.