Gate driving circuit and display device

A display device comprising:

• a display panel including a plurality of gate lines;
• and
• a gate driving circuit configured to drive the plurality of gate lines,
• wherein,
• the gate driving circuit includes:
• a first gate output buffer circuit including a first pull-up transistor and a first pull-down transistor;
• and
• a control circuit configured to control a voltage of a Q node connected to a gate node of the first pull-up transistor and a voltage of a QB node connected to a gate node of the first pull-down transistor,
• the first pull-up transistor is connected between a first clock signal input node and a first gate output node, and the first pull-down transistor is connected between the first gate output node and a first low level voltage node, and
• the control circuit includes:
• a first transistor connected between a first driving voltage node and the QB node;
• two second transistors connected in series between the QB node and a second low level voltage node;
• a third transistor connected between a connection node of the two second transistors and the first driving voltage node, the third transistor having a gate node connected to the QB node;
• a fourth transistor connected between a gate node of the first transistor and the first driving voltage node;
• and
• two fifth transistors connected in series between the gate node of the first transistor and the second low level voltage node.

A display device comprising:

• a display panel including a gate line;
• and
• a gate driving circuit which, in operation, drives the gate line, the gate driving circuit including:
• a gate output buffer circuit coupled to the gate line, the gate output buffer circuit including:
• a pull-up transistor having a gate node connected to a Q node;
• and
• a pull-down transistor having a gate node connected to a QB node;
• and
• a control circuit including a first transistor coupled to the QB node, the control circuit, in operation:
• applying a second low level voltage of a second low level voltage node to a gate node of the first transistor and a source node of the first transistor when voltage of the Q node is at a first level;
• and
• electrically isolating the second low level voltage node from the gate node of the first transistor when a ripple in the voltage of the Q node is applied to a gate node of a second transistor connected between the gate node of the first transistor and the second low level voltage node.