Chipset for frame rate control and associated signal processing method

A chipset for frame rate control (FRC), comprising:

• a first FRC chip, configured to receive input image data, and perform a motion compensation on a first part of the input image data to generate a first part of an output image data, wherein a frame rate of the output image data is greater than or equal to a frame rate of the input image data;
• and
• a second FRC chip, configured to receive a second part of the input image data, and perform the motion compensation on the second part of the input image data to generate a second part of the output image data;
• wherein the first part of the output image data and the second part of the output image data are combined into complete output image data for displaying on a display panel;
• wherein the first FRC chip comprises:
• an image splitting circuit, configured to receive the input image data, and split the input image data into the first part of the input image data and the second part of the input image data, wherein the second part of the input image data is sent to the second FRC chip;
• a memory, configured to store the first part of the input image data;
• a motion estimation circuit, configured to perform motion estimation on the input image data to generate motion information;
• and
• a motion compensation circuit, coupled to the memory, configured to read the first part of the input image data from the memory, and perform the motion compensation on the first part of the input image data to generate the first part of the output image data according to a first part of the motion information.

An image processing method, comprising:

• using a first frame rate control (FRC) chip to receive input image data, and split the input image data into a first part of the input image data and a second part of the input image data;
• storing the first part of the input image data into a memory within the first FRC chip;
• sending the second part of the input image data to a second FRC chip;
• using the first FRC chip to perform a motion compensation on the first part of the input image data to generate a first part of an output image data, wherein a frame rate of the output image data is greater than or equal to a frame rate of the input image data;
• and
• using the second FRC chip to perform the motion compensation on the second part of the input image data to generate a second part of the output image data;
• wherein the first part of the output image data and the second part of the output image data are combined into complete output image data for displaying on a display panel.