Circuitry and method
AssigneeArm Limited
InventorsHarsha Valsaraju, Javier Diaz Bruguera
Life of this patent
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Abstract
Circuitry comprises ray tracing circuitry comprising a plurality of floating-point circuitries to perform floating-point processing operations to detect intersection between a virtual ray defined by a ray direction and a test region, the floating-point circuitries operating to a given precision to generate an output floating-point value comprising a significand and an exponent; in which at least some of the plurality of floating-point circuitries are configured to round using a predetermined directed rounding mode any denormal floating-point value generated by operation of that circuitry so as to output normal values, a denormal floating-point value being a floating-point value in which the significand comprises one or more leading zeroes.
Claims18
Circuitry comprising:
- ray tracing circuitry comprising a plurality of floating-point circuitries to perform floating-point processing operations to detect intersection between a virtual ray defined by a ray direction and a test region, the floating-point circuitries operating to a given precision to generate an output floating-point value comprising a significand and an exponent, wherein:
- at least some of the plurality of floating-point circuitries are configured to round using a predetermined directed rounding mode each denormal floating-point value generated during the floating-point processing operations so as to output a normal value, a denormal floating-point value being a floating-point value in which the significand comprises one or more leading zeroes, and
- in at least some of the plurality of floating-point circuitries, the predetermined directed rounding mode is round-to-zero.
A method comprising:
- performing ray tracing circuitry by a plurality of floating-point processing operations to detect intersection between a virtual ray defined by a ray direction and a test region, the floating-point processing operations operating to a given precision to generate an output floating-point value comprising a significand and an exponent;
- for at least some of the plurality of floating-point circuitries, rounding using a predetermined directed rounding mode each denormal floating-point value generated during the floating-point processing operation so as to output a normal value, a denormal floating-point value being a floating-point value in which the significand comprises one or more leading zeroes;
- and
- in at least some of the plurality of floating-point circuitries, the predetermined directed rounding mode is round-to-zero.
Dependencies are inferred from the claim text.