Inter-processor data transfer in a machine learning accelerator, using statically scheduled instructions

A non-transitory computer readable storage medium storing instructions for generating a computer program containing instructions, the instructions implementing a machine learning network on a machine learning accelerator (MLA), the MLA comprising a plurality of interconnected processing elements implemented on a semiconductor die, the processing elements executing the instructions stored in memory on the MLA, the instructions when executed by one or more processors causing the one or more processors to perform steps including:

• receiving a description of the machine learning network;
• accessing a description of a topology of interconnections between processing elements;
• allocating computations that implement the machine learning network to processing elements for execution;
• determining data transfers for transfer of data to or from processing elements in order to execute the computations, the data transfers determined based on the topology of the interconnections between the processing elements;
• generating a computer program comprising compute instructions that implement the computations and data transfer instructions that implement the data transfers, the compute instructions and the data transfer instructions executed by the processing elements from the memory on the MLA, wherein generating the computer program comprises:
• determining non-conflicting data transfer paths for the data transfers based on the topology of the interconnections between processing elements, on dependencies of the instructions and on a duration for execution of the instructions;
• wherein each data transfer path specifies a routing and a time slot for the data transfer;
• generating data transfer instructions that specify routing of the data transfers;
• and
• generating a static schedule that schedules execution of the data transfer instructions during the time slots for the data transfers, the static schedule also scheduling execution of the compute instructions, wherein an execution order of the statically scheduled data transfer instructions and compute instructions by the processing elements does not depend on run-time conditions, branching or values of inputs to the instructions;
• and
• outputting the computer program.