Apparatus and method for dynamic control of microprocessor configuration
AssigneeIntel Corporation
InventorsAnkush Varma, Nikhil Gupta, Vasudevan Srinivasan, Krishnakanth Sistla, Nilanjan Palit, Abhinav Karhu, Eugene Gorbatov, Eliezer Weissmann
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Abstract
An apparatus and method for intelligently scheduling threads across a plurality of logical processors. For example, one embodiment of a processor comprises: a plurality of cores; one or more peripheral component interconnects to couple the plurality of cores to memory, and in response to a core configuration command to deactivate a core of the plurality of cores, a region within the memory is updated with an indication of deactivation of the core.
Claims18
A processor comprising:
- a plurality of cores;
- and
- one or more interconnects to couple the plurality of cores to memory;
- wherein in response to a core configuration command to deactivate a core of the plurality of cores, a region within the memory is updated with an indication of deactivation of the core, and
- wherein an interrupt is generated to indicate that the region within the memory is updated with the indication of deactivation of the core.
A method comprising:
- coupling a plurality of cores to memory of a processor via one or more interconnects;
- in response to a core configuration command to deactivate a core of the plurality of cores updating a region within the memory with an indication of deactivation of the core;
- and
- generating an interrupt to indicate that the region within the memory is updated with the indication of deactivation of the core.
A non-transitory machine-readable medium having program code stored thereon which, when executed by a machine, is capable of causing the machine to perform:
- coupling a plurality of cores to memory of a processor via one or more interconnects;
- in response to a core configuration command to deactivate a core of the plurality of cores updating a region within the memory with an indication of deactivation of the core, and
- generating an interrupt to indicate that the region within the memory is updated with the indication of deactivation of the core.
Dependencies are inferred from the claim text.