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US 11,886,884 B2Granted
Branch prediction based on coherence operations in processors
AssigneeIntel Corporation
InventorsChristopher Wilkerson, Binh Pham, Patrick Lu, Jared Warner Stark, IV
Life of this patent
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Abstract
In an embodiment, a processor includes a branch prediction circuit and a plurality of processing engines. The branch prediction circuit is to: detect a coherence operation associated with a first memory address; identify a first branch instruction associated with the first memory address; and predict a direction for the identified branch instruction based on the detected coherence operation. Other embodiments are described and claimed.
Claims21
A processor comprising:
- decoder circuitry to decode a branch instruction associated with coherence-based prediction, the branch instruction including a first operand to specify a target address and a second operand to specify a snoop address, wherein coherence-based prediction comprises branch prediction based on one or more coherence operations, wherein each coherence operation comprises a request to maintain coherency among copies of data elements included in a plurality of processing engines of the processor;
- and
- branch prediction circuitry to, in response to an execution of the branch instruction associated with coherence-based prediction, populate a first entry of a tracking data structure based on the target address and the snoop address specified in the branch instruction, the tracking data structure for coherence-based prediction.
A method comprising:
- decoding, by decoder circuitry of a processor, a branch instruction associated with coherence-based prediction, the branch instruction including a first operand to specify a target address and a second operand to specify a snoop address, wherein coherence-based prediction comprises branch prediction based on one or more coherence operations, wherein each coherence operation comprises a request to maintain coherency among copies of data elements included in a plurality of processing engines of the processor;
- executing the branch instruction;
- and
- in response to an execution of the branch instruction, populating a first entry of a tracking data structure based on the target address and the snoop address specified in the branch instruction, the tracking data structure for coherence-based prediction.
1 more element
A system comprising:
- a processor comprising:
- decoder circuitry to decode a branch instruction associated with coherence-based prediction, the branch instruction including a first operand to specify a target address and a second operand to specify a snoop address, wherein coherence-based prediction comprises branch prediction based on one or more coherence operations, wherein each coherence operation comprises a request to maintain coherency among copies of data elements included in a plurality of processing engines of the processor;
- and
- branch prediction circuitry to, in response to an execution of the branch instruction, populate a first entry of a tracking data structure based on the target address and the snoop address specified in the branch instruction, the tracking data structure for coherence-based prediction;
- and
- a memory coupled to the processor.
3 more elements
Dependencies are inferred from the claim text.