Dependency skipping in a load-compare-jump sequence of instructions by incorporating compare functionality into the jump instruction and auto-finishing the compare instruction

A method of performing instructions in a computer processor architecture, comprising:

• determining that a load instruction is being dispatched;
• writing destination related data of the load instruction into a mapper of the architecture;
• determining that a compare immediate instruction is being dispatched;
• determining that a branch conditional instruction is being dispatched;
• reading the mapper for load instruction destination related data;
• writing the load instruction destination related data into the compare immediate instruction;
• using the load instruction destination related data by the compare immediate instruction, during a finish of the compare immediate instruction;
• configuring the branch conditional instruction to wait until the load instruction produces a result before the branch conditional instruction issues and executes, wherein:
• the branch conditional instruction is executed without waiting for a finish of the compare immediate instruction;
• execution of the branch conditional instruction comprises performing a comparison with the destination related data of the load instruction;
• and
• the finish of the compare immediate instruction is an auto-finish step triggered in response to the branch conditional instruction being dispatched;
• accessing the load instruction destination related data in the compare immediate instruction in response to the conditional branch instruction being dispatched for auto-finishing of the compare immediate instruction;
• and
• sending the load instruction destination related data in the compare immediate instruction to a finish logic without waiting for the finish of the compare immediate instruction.

A computer processor architecture, comprising:

• a dispatch module configured to:
• determine that a load instruction is being dispatched;
• write destination related data of the load instruction into a mapper of the architecture;
• determine that a compare immediate instruction is being dispatched;
• determine that a branch conditional instruction is being dispatched;
• and
• configure the branch conditional instruction to wait until the load instruction produces a result before the branch conditional instruction issues and executes, wherein:
• the branch conditional instruction is executed without waiting for a finish of the compare immediate instruction;
• and
• execution of the branch conditional instruction comprises performing a comparison with the destination related data of the load instruction.