Pipelines for secure multithread execution

A method comprising:

• fetching a first instruction of a first thread from a memory into a processor pipeline that is configured to execute instructions from two or more threads in parallel using execution units of the processor pipeline;
• detecting that the first instruction has been dispatched into a pipeline stage of the processor;
• responsive to detection of dispatch of the first instruction, disabling dispatch of instructions of threads other than the first thread into one or more predetermined pipeline stages of the processor pipeline during execution of the first instruction by an execution unit in at least one of the one or more predetermined pipeline stages of the processor pipeline while one or more of the instructions of threads other than the first thread remain in the processor pipeline;
• executing the first instruction using an execution unit of the processor pipeline;
• and
• responsive to completion of execution of the first instruction, enabling dispatch of instructions of threads other than the first thread into the one or more predetermined pipeline stages of the processor pipeline.

An integrated circuit for executing instructions, comprising:

• a simultaneous multithreading processor core including a processor pipeline configured to execute instructions from two or more threads in parallel using execution units of the processor pipeline;
• and
• a thread hazard circuitry configured to
• detect that a first instruction of a first thread has been dispatched into a pipeline stage of the processor pipeline,
• responsive to detection of dispatch of the first instruction, block instructions of a second thread from being dispatched into one or more predetermined pipeline stages of the processor pipeline during one or more clock cycles during which the first instruction is being executed by an execution unit in at least one of the one or more predetermined pipeline stages of the processor pipeline and during which one or more of the instructions of the second thread remain in the processor pipeline, and
• responsive to completion of execution of the first instruction, enable dispatch of instructions of threads other than the first thread into the one or more predetermined pipeline stages of the processor pipeline.

An integrated circuit for executing instructions, comprising:

• a processor pipeline configured to execute instructions from two or more threads in parallel using execution units of the processor pipeline;
• and
• means for managing dispatch of instructions, the managing comprising
• detecting that a first instruction of a first thread has been dispatched into a pipeline stage of the processor pipeline,
• responsive to detection of dispatch of the first instruction, blocking instructions of threads other than the first thread from being dispatched into one or more predetermined pipeline stages of the processor pipeline while the first instruction is being executed by an execution unit in at least one of the one or more predetermined stages of the processor pipeline and while one or more of the instructions of threads other than the first thread remain in the processor pipeline, and
• responsive to completion of execution of the first instruction, enabling dispatch of instructions of threads other than the first thread into the one or more predetermined pipeline stages of the processor pipeline.