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US 11,886,740 B2Granted
Command prioritization techniques for reducing latency in a memory system
AssigneeMicron Technology, Inc.
InventorsChristopher Joseph Bueb, Olivier Duval
Life of this patent
Estimating the term…
Abstract
Methods, systems, and devices for command prioritization techniques for reducing latency in a memory system are described. In some examples, a host system may receive a set of commands from one or more virtual machines to access a common memory system. The host system may store the set of command in a command queue associated with the memory system and arrange the set of command according to order that is based on one or more identified pattern of accessing sequential addresses in the set of commands. The host system may transmit the set of command to the memory system based on the order and the memory system may execute the commands according to the order.
Claims25
A method, comprising:
- receiving, by a host system and from one or more virtual machines associated with the host system, a plurality of commands to access a memory system common to the one or more virtual machines;
- storing, in a command queue of the host system associated with the memory system, the plurality of commands and a set of parameters associated with each command of the plurality of commands according to a first order;
- arranging, by the host system, the plurality of commands within the command queue from the first order to a second order that is based at least in part on one or more identified patterns of accessing sequential addresses in the plurality of commands;
- and
- transmitting the plurality of commands to the memory system based at least in part on the second order.
2 more elements
A method, comprising:
- receiving, from one or more virtual machines, a plurality of commands to access a memory system common to the one or more virtual machines;
- storing, in a command queue associated with the memory system, the plurality of commands and a set of parameters associated with each command of the plurality of commands;
- generating a set of identifiers, wherein each identifier of the set of identifiers identifies a respective logical address range of a subset of logical address ranges of the memory system, wherein arranging the plurality of commands is based at least in part on the generating;
- arranging the plurality of commands according to an order that is based at least in part on one or more identified patterns of accessing sequential addresses in the plurality of commands;
- transmitting the plurality of commands to the memory system based at least in part on the order;
- measuring a duration between the memory system beginning to perform a first command of the plurality of commands and the memory system beginning to perform a second command of the plurality of commands, wherein the first command and the second command are performed consecutively;
- and
- updating the set of identifiers and respective logical address ranges based at least in part on the duration satisfying a threshold.
5 more elements
An apparatus, comprising:
- a controller configured to cause the apparatus to:
- receive, by a host system and from one or more virtual machines associated with the host system, a plurality of commands to access a memory system common to the one or more virtual machines;
- store, in a command queue of the host system associated with the memory system, the plurality of commands and a set of parameters associated with each command of the plurality of commands according to a first order;
- arrange, by the host system, the plurality of commands within the command queue from the first order to a second order that is based at least in part on one or more identified patterns of accessing sequential addresses in the plurality of commands;
- and
- transmit the plurality of commands from the host system to the memory system based at least in part on the second order.
3 more elements
An apparatus, comprising:
- a controller configured to cause the apparatus to:
- receive, from one or more virtual machines, a plurality of commands to access a memory system common to the one or more virtual machines;
- store, in a command queue associated with the memory system, the plurality of commands and a set of parameters associated with each command of the plurality of commands;
- generate a set of identifiers, wherein each identifier of the set of identifiers identifies a respective logical address range of a plurality of logical address ranges of the memory system, wherein arranging the plurality of commands is based at least in part on the generating;
- arrange the plurality of commands according to an order that is based at least in part on one or more identified patterns of accessing sequential addresses in the plurality of commands;
- transmit the plurality of commands to the memory system based at least in part on the order;
- measure a duration between the memory system beginning to perform a first command of the plurality of commands and the memory system beginning to perform a second command of the plurality of commands, wherein the first command and the second command are performed consecutively;
- and
- update the set of identifiers and their respective logical address ranges based at least in part on the duration satisfying a threshold.
6 more elements
An apparatus, comprising:
- a hypervisor coupled to one or more virtual machines associated with a host system and coupled to a memory system;
- and
- an Input/Output (I/O) scheduler associated with the hypervisor and configured to cause the apparatus to:
- receive, by the host system and from the one or more virtual machines, a plurality of commands to access the memory system common to the one or more virtual machines;
- store, in a command queue of the host system associated with the memory system, the plurality of commands and a set of parameters associated with each command of the plurality of commands according to a first order;
- arrange, by the host system, the plurality of commands within the command queue from the first order to a second order that is based at least in part on one or more identified patterns of accessing sequential addresses in the plurality of commands;
- and
- transmit the plurality of commands to the memory system based at least in part on the second order.
5 more elements
Dependencies are inferred from the claim text.