Circuit for testing a memory and test method thereof
AssigneeChangxin Memory Technologies, Inc.
InventorCheng-Jer Yang
Life of this patent
Estimating the term…
Abstract
A circuit for testing a memory and a test method thereof are provided. According to the circuit for testing a memory provided by the present disclosure, a switch control circuit is connected between a discharge end and a negative bias signal end of a Sub Wordline Drive (SWD) and configured to input a trigger signal, so that potential of a Word Line (WL) signal end in a to-be-tested circuit meets a preset potential suspension range. Then, it is determined whether there is leakage behavior between the WL signal end and a Bit Line (BL) signal end in the to-be-tested circuit by detecting whether the present level state of a stored signal in the to-be-tested circuit is consistent with an initial level state. The to-be-tested circuit is a corresponding circuit in a single memory.
Claims11
A circuit for testing a memory, comprising:
- a switch control circuit, configured to input a trigger signal for triggering potential of a Word Line (WL) signal end in a to-be-tested circuit to meet a preset potential suspension range,
- wherein the switch control circuit is connected between a discharge end and a negative bias signal end of a Sub Wordline Drive (SWD), and the to-be-tested circuit is a corresponding circuit in a single memory;
- wherein the switch control circuit comprises:
- a signal input circuit and a transistor;
- wherein a first end of the transistor is connected with the discharge end, a second end of the transistor is connected with the negative bias signal end, and a control end of the transistor is connected with an output end of the signal input circuit;
- wherein the signal input circuit is a NAND gate element, an output end of the NAND gate element is connected with the control end of the transistor, a first input end of the NAND gate element is configured to input an Address Signal (RA), and a second input end of the NAND gate element is configured to input the trigger signal.
A method for testing a memory, applied to a circuit for testing a memory comprising a switch control circuit, the switch control circuit being connected between a discharge end and a negative bias signal end of a Sub Wordline Drive (SWD), the method comprising:
- initializing a to-be-tested circuit, so that a stored signal of the to-be-tested circuit and voltage value of a Bit Line (BL) signal end meet a preset test condition, the to-be-tested circuit being a corresponding circuit in a single memory;
- inputting a trigger signal through the switch control circuit to trigger potential of a Word Line (WL) signal end in the to-be-tested circuit to meet a preset potential suspension range;
- and
- determining that there is leakage behavior between the WL signal end and the BL signal end in the to-be-tested circuit when it is detected that a present level state of the stored signal is inconsistent with an initial level state within preset time length.
Dependencies are inferred from the claim text.