US 11,886,702 B2 · Speed bins to support memory compatibility

Abstract

Methods, systems, and devices for speed bins to support memory compatibility are described. A host device may read a value of a register including serial presence detect data of a memory module. The serial presence detect data may be indicative of a timing constraint for operating the memory module at a first clock rate, where the timing constraint and the first clock rate may be associated with a first speed bin. The host device may select, for communication with the memory module, a second speed bin associated with a second clock rate at the host device and the timing constraint, where the host device may support operations according to a set of timing constraints that includes a set of values. The timing constraint may be selected from a subset of the set of timing constraints, where the subset may be exclusive of at least one of the set of values.

Claims35

Dependent claims

A method at a host device, comprising:

reading, by the host device, a value of a register comprising serial presence detect (SPD) data of a first memory module, the SPD data indicative of a timing constraint for operating the first memory module at a corresponding first clock rate, the timing constraint and the corresponding first clock rate associated with a first speed bin;
selecting, for communication with the first memory module, a second speed bin associated with a second clock rate at the host device and the timing constraint, wherein the host device supports operations according to a set of timing constraints that comprises a plurality of values, and wherein the timing constraint is selected from a subset of the set of timing constraints, the subset exclusive of at least one of the plurality of values;
and
communicating with the first memory module according to the second speed bin.

1 more element

An apparatus, comprising:

a circuit configured to cause the apparatus to:
read, by the apparatus, a value of a register comprising serial presence detect (SPD) data of a first memory module, the SPD data indicative of a timing constraint for operating the first memory module at a corresponding first clock rate, the timing constraint and the first clock rate associated with a first speed;
select, for communication with the first memory module, a second speed bin associated with a second clock rate at the apparatus and the timing constraint, wherein the apparatus supports operations according to a set of timing constraints that comprises a plurality of values, and wherein the timing constraint is selected from a subset of the set of timing constraints, the subset exclusive of at least one of the plurality of values;
and
communicate with the first memory module according to the second speed bin.

2 more elements

A non-transitory computer-readable medium comprising instructions which, when executed by a processor of an electronic device, cause the electronic device to:

read, by a host device, a value of a register comprising serial presence detect (SPD) data of a first memory module, the SPD data indicative of a timing constraint for operating the first memory module at a corresponding first clock rate, the timing constraint and the corresponding first clock rate associated with a first speed;
select, for communication with the first memory module, a second speed bin associated with a second clock rate at the host device and the timing constraint, wherein the host device supports operations according to a set of timing constraints that comprises a plurality of values, and wherein the timing constraint is selected from a subset of the set of timing constraints, the subset exclusive of at least one of the plurality of values;
and
communicate with the first memory module according to the second speed bin.

1 more element

Dependencies are inferred from the claim text.

Speed bins to support memory compatibility

Life of this patent

Speed bins to support memory compatibility

Life of this patent

Abstract

Claims35