Computer architecture with resistive processing units
AssigneeInternational Business Machines Corporation
InventorTayfun Gokmen
Life of this patent
Estimating the term…
Abstract
A processor includes an array of resistive processing units connected between row and column lines with a resistive element. A first single instruction, multiple data processing unit (SIMD) is connected to the row lines. A second SIMD is connected to the column lines. A first instruction issuer is connected to the first SIMD to issue instructions to the first SIMD, and a second instruction issuer is connected to the second SIMD to issue instructions to the second SIMD such that the processor is programmable and configurable for specific operations depending on an issued instruction set.
Claims20
A processor device, comprising:
- an array of single resistive cross point processing units connected between row and column lines with a resistive element, the array of single resistive cross point processing units being analog processing elements cross-coupled between the row and column lines, and configured to perform bidirectional communications along the row and column lines using the array of single resistive cross point processing units and to execute analog computations at a core in tandem with programmable peripheral circuitry.
A processor device, comprising:
- a first core including a first array of single resistive cross point processing units connected between row and column lines with a resistive element, the first array of single resistive cross point processing units being analog processing elements cross-coupled between the row and column lines, and configured to perform bidirectional communications along the row and column lines using the first array of single resistive cross point processing units and to execute analog computations at the first core in tandem with programmable peripheral circuitry;
- and
- a second core including a second array of resistive processing units connected between row and column lines with a resistive element.
A computer-implemented processing method, comprising:
- issuing coded instructions to carry out a processing operation using an array of single resistive cross point processing units connected between row and column lines with a resistive element, the array of single resistive cross point processing units being analog processing elements cross-coupled between the row and column lines, and configured to perform bidirectional communications along the row and column lines using the array of single resistive cross point processing units and to execute analog computations at a core in tandem with programmable peripheral circuitry.
Dependencies are inferred from the claim text.