Reconfigurable arithmetic engine circuit

A plurality of reconfigurable arithmetic circuits arranged in an array, each reconfigurable arithmetic circuit, of the plurality of reconfigurable arithmetic circuits, comprising:

• a plurality of input reordering queues configured to store a plurality of inputs, the plurality of input reordering queues comprising input reordering logic circuitry configured to reorder a sequence of the plurality of inputs of a reconfigurable arithmetic circuit and an adjacent reconfigurable arithmetic circuit of the plurality of reconfigurable arithmetic circuits;
• a multiplier shifter and combiner network coupled to the plurality of input reordering queues;
• an accumulator circuit;
• at least one control logic circuit coupled to the multiplier shifter and combiner network and to the accumulator circuit;
• a plurality of output reorder queues configured to reorder outputs from the reconfigurable arithmetic circuit and the adjacent reconfigurable arithmetic circuit of the plurality of reconfigurable arithmetic circuits;
• and
• a configurable interconnection network coupled to the multiplier shifter and combiner network, the configurable interconnection network configurable to interconnect at least two reconfigurable arithmetic circuits, of the plurality of reconfigurable arithmetic circuits, to perform double precision multiply-adds, single precision single cycle complex multiply, Fast Fourier Transform (“FFT”) butterfly, exponent resolution, multiply-accumulate, and one or more logic operations.

A reconfigurable arithmetic circuit comprising:

• a plurality of data inputs, the plurality of data inputs comprising a first, X data input;
• a second, Y data input, and a third, Z data input;
• a plurality of data outputs;
• a plurality of output reorder queues coupled to the plurality of data outputs, the plurality of output reorder queues configurable to reorder output data;
• a plurality of input reordering queues coupled to the plurality of data inputs and configured to store input data, the input reordering queues further comprising input reordering logic circuitry configurable to reorder a sequence of the input data;
• a configurable multiplier coupled to the plurality of input reordering queues, the configurable multiplier having a plurality of operating modes, the plurality of operating modes comprising a fixed point operating mode and a floating point operating mode, wherein the configurable multiplier has a native operating mode of a 27×27 unsigned multiplier further configurable to process signed inputs, and further configurable to become four 8×8 multipliers, two 16×16 single-instruction multiple-data (SIMD) multipliers, one 32×32 multiplier and one 54×54 multiplier;
• a multiplier shifter and combiner network coupled to the configurable multiplier, the multiplier shifter and combiner network comprising:
• a shifter circuit;
• a plurality of series-coupled adder circuits coupled to the shifter circuit;
• and
• a plurality of direct connections coupling the multiplier shifter and combiner network to one or more adjacent reconfigurable arithmetic circuits to perform single cycle 32×32 multiplication, single cycle 54×54 multiplication, single precision/24×24 multiplication, and single-instruction multiple-data (SIMD) dot products;
• a fixed and floating point carry-save accumulator circuit;
• and
• a plurality of control logic circuits coupled to the multiplier shifter and combiner network and to the accumulator circuit, the plurality of control logic circuits comprising:
• a compare circuit configurable to extract a minimum or maximum data value from an input data stream and an index from the input data stream, and is further configurable to compare two input data streams, to swap the two input data streams to put the minimum of the two input data streams on a first output and the maximum of the two input data streams on a second output, to perform data steering, to generate address sequences, and to generate comparison flags for equality, greater than and less than;
• a Boolean logic circuit comprising an AND-OR-INVERT logic unit configurable to perform AND, NAND, OR, NOR, XOR, XNOR, and selector operations on 32-bit integer inputs;
• a Z input shifter configurable to shift a floating point Z-input value to a radix-32 exponent value, to shift by multiples of 32-bits to match a scaling of multiplier sum outputs, and having has a plurality of integer modes wherein the Z input shifter is configurable as a shifter or rotator with 64, 32, 2×16 and 4×8 bit shift or rotate modes;
• an exponent logic circuit;
• and
• an add, saturate and round circuit.

A reconfigurable arithmetic circuit comprising:

• a plurality of input reordering queues;
• a multiplier shifter and combiner network, the multiplier shifter and combiner network comprising:
• a shifter circuit;
• and
• a plurality of series-coupled adder circuits coupled to the shifter circuit;
• a configurable multiplier having a plurality of operating modes, the configurable multiplier coupled to the plurality of input reordering queues and to the multiplier shifter and combiner network, the plurality of operating modes comprising a fixed point operating mode and a floating point operating mode, wherein the configurable multiplier has a native operating mode of a 27×27 unsigned multiplier further configurable to process signed inputs, the configurable multiplier further configurable as four 8×8 multipliers, two 16×16 single-instruction multiple-data (SIMD) multipliers, one 32×32 multiplier, and one 54×54 multiplier;
• an accumulator circuit;
• and
• at least one control logic circuit coupled to the multiplier shifter and combiner network and to the accumulator circuit.

A reconfigurable arithmetic circuit comprising:

• a plurality of input reordering queues configured to store a plurality of inputs, the plurality of input reordering queues further comprising:
• input reordering logic circuitry configured to reorder a sequence of the plurality of inputs, and further configurable to adjust a sign bit for negate and absolute value functions, to de-interleave in-phase (“I”) and quadrature (“Q”) data inputs, and to de-interleave odd and even data inputs;
• a multiplier shifter and combiner network coupled to the plurality of input reordering queues, the multiplier shifter and combiner network comprising:
• a shifter circuit;
• and
• a plurality of series-coupled adder circuits coupled to the shifter circuit;
• an accumulator circuit;
• and
• at least one control logic circuit coupled to the multiplier shifter and combiner network and to the accumulator circuit.