Apparatus and methods for burst communications within die architectures

A method by a processor comprising:

• receiving a first data transfer request over a first communication bus;
• determining a final address based on the first data transfer request;
• asserting a chip select signal of a second communication bus in response to the first data transfer request;
• while asserting the chip select signal:
• initiating a first data exchange over the second communication bus;
• receiving a second data transfer request over the first communication bus;
• determining an initial address based on the second data transfer request;
• determining to continue to assert the chip select signal based on the initial address and the final address;
• and
• initiating a second data exchange over the second communication bus while the chip select signal is asserted.

A non-transitory, machine-readable storage medium comprises instructions that, when executed by at least one processor, cause the at least one processor to:

• receive a first data transfer request over a first communication bus;
• determine a final address based on the first data transfer request;
• assert a chip select signal of a second communication bus in response to the first data transfer request;
• and
• while asserting the chip select signal:
• initiate a first data exchange over the second communication bus;
• receive a second data transfer request over the first communication bus;
• determine an initial address based on the second data transfer request;
• determine to continue to assert the chip select signal based on the initial address and the final address;
• and
• initiate a second data exchange over the second communication bus while the chip select signal is asserted.

A die package, comprising:

• a processor;
• and
• controller logic electrically coupled to the processor over a first communication bus, the controller logic configured to:
• receive a first data transfer request from the processor over the first communication bus;
• determine a final address based on the first data transfer request;
• assert a chip select signal of a second communication bus in response to the first data transfer request;
• and
• while asserting the chip select signal:
• initiate a first data exchange over the second communication bus;
• receive a second data transfer request from the processor over the first communication bus;
• determine an initial address based on the second data transfer request;
• determine to continue to assert the chip select signal based on the initial address and the final address;
• and
• initiate a second data exchange over the second communication bus while the chip select signal is asserted.