Memory controller and operating method thereof
AssigneeSK hynix Inc.
InventorsYoung Jo Kim, Sung Yeob Cho
Life of this patent
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Abstract
A memory controller having an improved operating speed controls a memory device in response to a request from a host. The memory controller includes: a processor for driving firmware for controlling communication between the host and the memory device; a map data receiver for receiving map data including a plurality of mapping entries including physical block addresses, for operations to be performed on the memory device from the memory device under the control of the processor; and a map data controller for checking a mapping entry corresponding to the request, which are received from the map data receiver, snooping the detected mapping entry and outputting the detected mapping entry to the processor.
Claims16
A memory controller for controlling a memory device in response to a read request from a host, the memory controller comprising:
- a buffer memory;
- a map data controller;
- a map data receiver configured to communicate with the memory device;
- and
- a processor configured to receive the read request, and to control the map data receiver to, receive a plurality of mapping entries included in map data read from the memory device, transfer the plurality of mapping entries to both the buffer memory and the map data controller, and provide a requested logical block address corresponding to the read request to the map data controller,
- wherein the map data controller, concurrently with the plurality of mapping entries being transferred to the buffer memory, is configured to detect a mapping entry of the requested logical block address among the plurality of mapping entries, and to output an interrupt signal to the processor in response to detection of the mapping entry of the requested logical block address.
A method for operating a memory controller for controlling a memory device in response to a read request from a host, the method comprising:
- receiving map data including a plurality of mapping entries read from the memory device;
- transferring the plurality of mapping entries to both a buffer memory and a map data controller included in the memory controller;
- concurrently with transferring the plurality of mapping entries to the buffer memory, detecting, by the map data controller, a mapping entry of a requested logical block address corresponding to the read request among the plurality of mapping entries;
- and
- outputting, by the map data controller, an interrupt signal representing that the mapping entry of the requested logical block address has been detected in response to detection of the mapping entry of the requested logical block address.
An operating method of a memory controller, the operating method comprising:
- transferring plural map entries read from a memory device to both a buffer memory and a map data controller included in the memory controller, each map entry representing a mapping relationship between a logical address and a physical address;
- concurrently with transferring the plural map entries to the buffer memory, detecting, by the map data controller, in order outputted during the transferring, a map entry having a requested logical address provided from the host among the plural map entries;
- outputting, by the map data controller, an interrupt signal to a processor included in the memory controller when the map entry having the requested logical address is detected;
- and
- controlling the memory device to perform an operation according to the map entry having the requested logical address in response to a read request provided along with the requested logical address from the host.
Dependencies are inferred from the claim text.