Hybrid victim cache and write miss buffer with fence operation
AssigneeTexas Instruments Incorporated
InventorsNaveen Bhoria, Timothy David Anderson, Pete Hippleheuser
Life of this patent
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Abstract
A caching system including a first sub-cache, and a second sub-cache, coupled in parallel with the first cache, for storing cache data evicted from the first sub-cache and write-memory commands that are not cached in the first sub-cache, and wherein the second sub-cache includes: color tag bits configured to store an indication that a corresponding cache line of the second sub-cache storing write miss data is associated with a color tag, and an eviction controller configured to evict cache lines of the second sub-cache storing write-miss data based on the color tag associated with the cache line.
Claims19
A caching system comprising:
- a first sub-cache configured to couple to a processor;
- and
- a second sub-cache configured to couple to the processor such that the first sub-cache and the second sub-cache are in parallel, wherein the second sub-cache includes:
- a set of cache lines each configured to store:
- cache data evicted from the first sub-cache, and
- data associated with write-memory commands which miss in the first sub-cache;
- a set of color tag bits configured to store a respective indication for each cache line of the set of cache lines that the corresponding cache line is associated with a respective process;
- and
- an eviction controller configured to evict data from the second sub-cache based on the set of color tag bits.
A method for caching data, comprising:
- receiving, by a caching system, a write memory command for a memory address;
- determining, by a first sub-cache of the caching system, that the memory address is not cached in the first sub-cache;
- determining, in parallel with the first sub-cache and by a second sub-cache of the caching system, that the memory address is not cached in the second sub-cache, wherein the second sub-cache is configured to store:
- cache data evicted from the first sub-cache, and
- data associated with write-memory commands which miss in the first sub-cache;
- storing data associated with the write memory command in the second sub-cache;
- storing, in the second sub-cache, a color tag bit associated with the stored data that indicates a process associated with the stored data;
- and
- evicting the stored data based on the color tag bit.
A device comprising:
- a processor;
- a first sub-cache coupled to the processor;
- and
- a second sub-cache coupled to the processor in parallel with the first sub-cache that includes:
- a set of cache lines each configured to store:
- cache data evicted from the first sub-cache, and
- data associated with write-memory commands which miss in the first sub-cache:
- a set of color tag bits configured to store a respective indication for each cache line of the set of cache lines that the corresponding cache line is associated with a respective process;
- and
- an eviction controller configured to evict data from the second sub-cache based on the set of color tag bits.
Dependencies are inferred from the claim text.