Access friendly memory architecture of graph neural network sampling
AssigneeT-Head (Shanghai) Semiconductor Co., Ltd.
InventorsHeng Liu, Tianchan Guan, Shuangchen Li, Hongzhong Zheng
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Abstract
This specification describes methods and systems for accelerating attribute data access for graph neural network (GNN) processing. An example method includes: receiving a root node identifier corresponding to a node in a graph for GNN processing; determining one or more candidate node identifiers according to the root node identifier, wherein attribute data corresponding to the one or more candidate node identifiers are sequentially stored in a memory; and sampling one or more graph node identifiers at least from the one or more candidate node identifiers for the GNN processing.
Claims20
A computer-implemented method, comprising:
- receiving a root node identifier corresponding to a root node in a graph for graph neural network (GNN) processing;
- determining a plurality of node identifiers for a plurality of nodes in the graph according to locations of the plurality of nodes in the graph relative to the root node;
- mapping the plurality of node identifiers respectively to physical memory addresses in a memory, wherein:
- each of the physical memory addresses in the memory stores attribute data of the node identified by the corresponding node identifier, and
- each of the physical memory addresses comprises a memory bank identifier of a memory bank, wherein each memory bank stores a plurality of rows, columns, or memory pages;
- selecting, based on the memory bank identifiers of the physical memory addresses, a subset of the physical memory addresses that maximizes intra-memory-bank sequential memory access;
- de-mapping the selected subset of the physical memory addresses into corresponding node identifiers to obtain one or more candidate node identifiers;
- and
- sampling one or more graph node identifiers at least from the one or more candidate node identifiers for the GNN processing.
A system for accelerating Graph Neural Network (GNN) attribute access, comprising:
- a memory configured to store attribute data of graph nodes in a graph;
- and
- a GNN accelerator configured to:
- receive a root node identifier corresponding to a node in the graph for GNN processing;
- determine a plurality of node identifiers for a plurality of nodes in the graph according to locations of the plurality of nodes in the graph relative to the root node;
- map the plurality of node identifiers respectively to physical memory addresses in a memory, wherein:
- each of the physical memory addresses in the memory stores attribute data of the node identified by the corresponding node identifier, and
- each of the physical memory addresses comprises a memory bank identifier of a memory bank, wherein each memory bank stores a plurality of rows, columns, or memory pages;
- select, based on the memory bank identifiers of the physical memory addresses, a subset of the physical memory addresses that maximizes intra-memory-bank sequential memory access;
- de-map the selected subset of the physical memory addresses into corresponding node identifiers to obtain one or more candidate node identifiers;
- and
- sample one or more graph node identifiers at least from the one or more candidate node identifiers for the GNN processing.
A graph neural network (GNN) accelerating device, comprising:
- an obtaining module configured to receive a root node identifier corresponding to a node in a graph for GNN processing;
- a determining module configured to:
- determine a plurality of node identifiers for a plurality of nodes in the graph according to locations of the plurality of nodes in the graph relative to the root node;
- map the plurality of node identifiers respectively to physical memory addresses in a memory, wherein:
- each of the physical memory addresses in the memory stores attribute data of the node identified by the corresponding node identifier, and
- each of the physical memory addresses comprises a memory bank identifier of a memory bank, wherein each memory bank stores a plurality of rows, columns, or memory pages;
- select, based on the memory bank identifiers of the physical memory addresses, a subset of the physical memory addresses that maximizes intra-memory-bank sequential memory access;
- and
- de-map the selected subset of the physical memory addresses into corresponding node identifiers to obtain one or more candidate node identifiers;
- and
- a sampling module configured to sample one or more graph node identifiers at least from the one or more candidate node identifiers for the GNN processing.
Dependencies are inferred from the claim text.