Interleaved cache prefetching
AssigneeMicron Technology, Inc.
InventorsLaurent Isenegger, Robert M. Walker, Cagdas Dirik
Life of this patent
Estimating the term…
Abstract
A method includes receiving, at a direct memory access (DMA) controller of a memory device, a first command from a first cache controller coupled to the memory device to prefetch first data from the memory device and sending the prefetched first data, in response to receiving the first command, to a second cache controller coupled to the memory device. The method can further include receiving a second command from a second cache controller coupled to the memory device to prefetch second data from the memory device, and sending the prefetched second data, in response to receiving the second command, to a third cache controller coupled to the memory device.
Claims20
A method, comprising:
- tracking, at a direct memory access (DMA) controller of a memory device, which source addresses are accessed by which cache controllers of a number of cache controllers;
- detecting access patterns of the number of cache controllers based on the tracked source addresses;
- anticipating future source address access based on the detected access patterns by prefetching associated data into a local buffer in the memory device;
- and
- sending prefetched data from a first cache controller of the number of cache controllers to a second cache controller of the number of cache controllers based on the anticipated future source address access.
A system, comprising:
- a memory device including a direct memory access (DMA) controller;
- a number of cache devices coupled to the memory device;
- a number of cache controllers coupled to the memory device;
- a local buffer;
- and
- a monitoring engine configured to:
- track which source addresses are accessed by which of the number of cache controllers;
- detect access patterns of the number of cache controllers based on the tracked source addresses;
- and
- anticipate future source address access based on the detected access patterns by prefetching associated data into the local buffer.
An apparatus, comprising:
- a number of cache controllers coupled to a memory device and configured to send commands to the memory device;
- the memory device coupled to a plurality of cache devices and comprising:
- a monitoring engine configured to:
- track which source addresses are accessed by which of the number of cache controllers;
- detect access patterns of the number of cache controllers based on the tracked source addresses;
- anticipate future source address access based on the detected access patterns by prefetching associated data into a local buffer of the memory device.
Dependencies are inferred from the claim text.