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AssigneeXi'an Jiaotong University
InventorsTian Xia, Pengju Ren, Haoran Zhao, Zehua Li, Wenzhe Zhao, Nanning Zheng
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Computing architecture comprises an off-chip memory, an on-chip cache unit, a prefetching unit, a global scheduler, a transmitting unit, a pre-recombination network, a post-recombination network, a main computing array, a write-back cache unit, a data dependence controller and an auxiliary computing array. The architecture reads data tiles into an on-chip cache in a prefetching mode, and performs computing according to the data tiles; in the computing process of the tiles, a tile exchange network is adopted to recombine a data structure, and a data dependence module is arranged to process a data dependence relationship possibly existing between different tiles. According to the computing architecture, the data utilization rate can be increased, the data processing flexibility is improved, and therefore Cache Miss is reduced, and the memory bandwidth pressure is reduced.
Computing architecture, comprising an off-chip memory, an on-chip cache unit, a transmitting unit, a pre-recombination network, a post-recombination network, a main computing array, a data dependence controller and a global scheduler, wherein
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