Server recovery from a change in storage control chip
AssigneeInternational Business Machines Corporation
InventorBurkhard Steinmacher-Burow
Life of this patent
Estimating the term…
Abstract
Configuring an address-to-SC unit (A2SU) of each of a plurality of CPU chips based on a number of valid SC chips in the computer system is disclosed. The A2SU is configured to correlate each of a plurality of memory addresses with a respective one of the valid SC chips. In response to detecting a change in the number of valid SC chips, pausing operation of the computer system including operation of a cache of each of the plurality of CPU chips; while operation of the computer system is paused, reconfiguring the A2SU in each of the plurality of CPU chips based on the change in the number of valid SC chips; and in response to reconfiguring the A2SU, resuming operation of the computer system.
Claims20
A method of recovering from a change in a number of storage control (SC) chips in a computer system, the method comprising:
- configuring an address to SC chip unit (A2SU) of each of a plurality of central processing unit (CPU) chips based on a number of valid SC chips in the computer system;
- in response to detecting a change in the number of valid SC chips, pausing operation of the computer system including operation of a cache of each of the plurality of CPU chips;
- while operation of the computer system is paused, reconfiguring the A2SU in each of the plurality of CPU chips based on the change in the number of valid SC chips;
- and
- in response to reconfiguring the A2SU, resuming operation of the computer system.
A computer system comprising:
- a plurality of central processing unit (CPU) boards, each CPU board including one or more physical CPU chips;
- a plurality of storage control (SC) boards, each SC board including at least one SC chip;
- and
- wherein each of the CPU chips includes a respective address to SC chip unit (A2SU) configured to correlate each of a plurality of memory addresses with a respective one of the SC chips on the plurality of SC boards;
- wherein, in response to detecting a change in the number of SC chips, operation of the computer system is paused including operation of a cache of each of the plurality of CPU chips;
- wherein each of the CPU chips is configured to reconfigure the respective A2SU based on the change in the number of SC chips while operation of the computer system is paused;
- and
- wherein operation of the computer system is resumed in response to reconfiguring the A2SU in each of the plurality of CPU chips.
A computer program product comprising a computer readable storage medium having a computer readable program stored therein, wherein the computer readable program, when executed by a processor on a first vehicle, causes the processor to:
- configure an address to storage control (SC) chip unit (A2SU) of each of a plurality of central processing unit (CPU) chips based on a number of valid SC chips in a computer system;
- in response to detecting a change in the number of valid SC chips, pause operation of the computer system including operation of a cache of each of the plurality of CPU chips;
- while operation of the computer system is paused, reconfigure the A2SU in each of the plurality of CPU chips based on the change in the number of valid SC chips;
- and
- in response to reconfiguring the A2SU, resume operation of the computer system.
Dependencies are inferred from the claim text.