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US 11,886,344 B2Granted
Cached system for managing state vectors
AssigneeXilinx, Inc.
InventorsNoel J. Brady, Lars-Olof B Svensson
Life of this patent
Estimating the term…
Abstract
A cache system includes a computational cache and a computational cache miss-handler. The computational cache is configured to cache state vectors and perform read-modify-write (RMW) operations on the cached state vectors responsive to received RMW commands. The computational cache miss-handler is configured to perform RMW operations on state vectors stored in a memory responsive to cache misses in the computational cache. The memory is external to the cache system.
Claims18
A system, comprising:
- a cache system including:
- a computational cache configured to cache state vectors and perform read-modify-write (RMW) operations on the cached state vectors responsive to received RMW commands;
- and
- a computational cache miss-handler configured to perform RMW operations on state vectors stored in a memory responsive to cache misses in the computational cache, wherein the memory is external to the cache system;
- wherein the computational cache miss-handler includes a thread assignment circuit configured to assign the RMW commands corresponding to cache misses to threads and an RMW coalescing circuit configured to combine selected RMW commands belonging to a same thread and having a same index into a single RMW command.
2 more elements
A method, comprising:
- receiving, within a cache system, a read-modify-write (RMW) command from a processor;
- and
- in response to the RMW command, performing, using the cache system, an RMW operation on a state vector specified by the RMW command without further involvement of the processor, wherein the performing includes:
- assigning the RMW command to a thread of a plurality of threads;
- storing the RMW command in a selected RMW command queue of a plurality of RMW command queues based on thread assignment;
- and
- executing the RMW command from the selected RMW command queue according to a round-robin arbitration technique where different ones of the plurality of RMW command queues correspond to different memory banks of a memory.
4 more elements
Dependencies are inferred from the claim text.