Characterizing error correlation based on error logging for computer buses
AssigneeIntel Corporation
InventorDebendra Das Sharma
Life of this patent
Estimating the term…
Abstract
Systems and devices can include forward error correction (FEC) logic to identify a correctable error in the first flit, and correct the correctable error using three error correcting code (ECC) groups. System and devices can also include an error log, the correctable error log to log a symbol number in the first flit corrected by each ECC group, and to log a magnitude of the correctable error corrected by each ECC group in the first flit; and a configuration register to log link error correlation, the link error correlation comprising a indication of one or more bits in error in the first flit.
Claims26
An apparatus comprising:
- a port to receive flow control units (flits) across a serial interconnect, the flits comprising a first flit and subsequent flits;
- and
- a protocol stack comprising:
- forward error correction (FEC) logic to identify a correctable error in the first flit using each of three error correcting code (ECC) groups, the FEC logic to correct the error using each of the ECC group;
- and
- an error log, the error log to log:
- a symbol number in the first flit corrected by each ECC group, and
- a magnitude of the error corrected by each ECC group in the first flit.
A method comprising:
- receiving a first flow control unit (flit) at a port across a serial interconnect, the first flit a first flit of a series of flits to be received by the port;
- determining a correctable error in the first flit;
- correcting the correctable error in the first flit by each of three of error correcting code (ECC) groups;
- recording a symbol number in the first flit corrected by each ECC group in an error log;
- and
- recording a magnitude of the error corrected by each ECC group in the first flit in the error log.
A system comprising:
- a hardware processor;
- a transmitter port for transmitting flow control units (flits) across a serial interconnect;
- a receiver port to receive flits from across a serial interconnect;
- a protocol stack comprising:
- forward error correction (FEC) logic to:
- identify a correctable error in a first flit, and
- correct the correctable error using three error correcting code (ECC) groups;
- and
- an error log, the correctable error log to log a symbol number in the first flit corrected by each ECC group, and to log a magnitude of the correctable error corrected by each ECC group in the first flit;
- and
- a configuration register to log link error correlation, the link error correlation comprising a indication of one or more bits in error in the first flit.
Dependencies are inferred from the claim text.