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US 11,886,291 B1Granted
Providing cache line metadata over multiple cache lines
AssigneeDell Products L.P.
InventorStuart Allen Berke
Life of this patent
Estimating the term…
Abstract
An information handling system utilizes data with a cache line size. A memory module is coupled to a memory controller by a memory bus, and stores and retrieves data with a memory line size. The cache line size is an integer multiple of the memory line size. The memory controller calculates error correction code data for each memory line of user data, and generates metadata related to the user data for chunks of data that are equal to an integer number (N) of cache lines, where N is greater than one.
Claims20
An information handling system, comprising:
- a processor configured to utilize data with a cache line size, the processor including a memory controller;
- and
- a memory module coupled to the memory controller by a memory bus, wherein the memory module is configured to store and retrieve data with a memory line size, wherein the cache line size is an integer multiple (A) of the memory line size;
- wherein the memory controller is configured to calculate error correction code (ECC) data for an integer number (B) of memory lines of user data, and to generate metadata related to the user data for chunks of data that are equal to an integer number (C) of cache lines, where B<A*C and C is greater than one.
1 more element
A method, comprising:
- coupling, by a memory bus, a memory module of an information handling system to a memory controller of a processor of the information handling system, wherein the processor is configured to utilize data with a cache line size, wherein the memory module is configured to store and retrieve data with a memory line size, and wherein the cache line size is an integer multiple (A) of the memory line size;
- calculating, by the memory controller, error correction code (ECC) data for an integer number (B) of memory lines of user data;
- and
- generating, by the memory controller, metadata related to the user data for chunks of data that are equal to an integer number (C) of cache lines, where B<A*C and C is greater than one.
1 more element
An information handling system, comprising:
- a processor configured to utilize data with a 64-byte cache line size, the processor including a memory controller;
- and
- a memory module coupled to the memory controller by a memory bus, wherein the memory module is configured to store and retrieve data with an 8-byte memory line size;
- wherein the memory controller is configured to calculate six (6) bits of error correction code data for each memory line of user data, and to generate 32-bits of metadata related to the user data for chunks of data that are equal to an two (2) cache lines.
1 more element
Dependencies are inferred from the claim text.