Optimize data protection layouts based on distributed flash wear leveling
AssigneePure Storage, Inc.
InventorsBrian Gold, Robert Lee, John Hayes
Life of this patent
Estimating the term…
Abstract
A method for storing data in a storage system having solid-state memory is provided. The method includes determining portions of the solid-state memory that have a faster access rate and portions of the solid-state memory that have a slower access rate, relative to each other or to a threshold. The method includes writing data bits of erasure coded data to the portions of the solid-state memory having the faster access rate, and writing one or more parity bits of the erasure coded data to the portions of the solid-state memory having the slower access rate. A storage system is also provided.
Claims20
A storage system, comprising:
- a plurality of storage nodes, each storage node of the plurality of storage nodes separate from other storage nodes and configurable to write data across the plurality of storage nodes, each portion of data having a plurality of data bits and one or more parity bits, and each storage node comprising a respective processing device and a respective memory;
- and
- each storage node of the plurality of storage nodes configurable to identify portions of memory of the plurality of storage nodes having a first access rate and portions of memory of the plurality of storage nodes having a second access rate, the first access rate faster than the second access rate;
- and
- each storage node of the plurality of storage nodes configurable to write the data bits to the portions of the memory having the first access rate and write the one or more parity bits to the portions of the memory having the second access rate.
A method, comprising:
- identifying portions of memory of a plurality of storage nodes that have a faster access rate and portions of the memory that have a slower access rate, relative to each other, each storage node separate from the other storage nodes and each storage node comprising a respective processing device and a respective memory;
- writing data bits of erasure coded data to the portions of the memory having the faster access rate;
- and
- writing one or more parity bits of the erasure coded data to the portions of the memory having the slower access rate.
A tangible, non-transitory, computer-readable media having instructions thereupon which, when executed by a processor, cause the processor to perform a method comprising:
- identifying portions of memory of a plurality of storage nodes that have a faster access rate and portions of the memory that have a slower access rate, relative to each other, each storage node separate from the other storage nodes and each storage node comprising a respective processing device and a respective memory;
- writing data bits of erasure coded data to the portions of the memory having the faster access rate;
- and
- writing one or more parity bits of the erasure coded data to the portions of the memory having the slower access rate.
Dependencies are inferred from the claim text.