US 11,886,228 B2 · Interface bus combining

Abstract

Circuits and methods enabling common control of an agent device by two or more buses, particularly MIPI RFFE serial buses. In essence, the invention provides flagging signals designating completed register write operations to denote which of two registers are active, such that synchronization is accomplished in a clock-free manner. One embodiment includes at least two decoders, each including a common register and a bus (S/P) decoder coupled to a respective bus and to the common register. The S/P decoder asserts a write-complete signal when a write operation to a corresponding common register is completed. A multiplexer has at least two selectable input bus ports coupled to the common registers within the at least two decoders. A selection circuit selects an input bus port of the multiplexer in response to the assertion of a last write-complete signal from the S/P decoders.

Claims19

Dependent claims

A circuit that enables common control of one or more agent devices by two or more buses using mutually exclusive arbitration, the circuit including:

(a) at least two decoders, each including:
(1) at least one common register;
(2) a bus decoder coupled to the at least one common register and configured to be coupled to a respective bus, the bus decoder configured to assert a write-complete signal when a write operation to a corresponding one of the at least one common register is completed;
(b) a multiplexer having at least two selectable input bus ports each coupled to one of the at least one common register within respective ones of the at least two decoders, and an output port configured to be coupled to at least one of the one or more agent devices;
and
(c) a selection circuit, coupled to two or more of the bus decoders and to the multiplexer, the selection circuit configured to select an input bus port of the multiplexer in response to the assertion of a last write-complete signal from the coupled bus decoders.

3 more elements

Dependencies are inferred from the claim text.

Interface bus combining

Life of this patent

Interface bus combining

Life of this patent

Abstract

Claims19