Ultra-low leakage test verification circuit
AssigneeAutomatic Timing & Controls, Inc.
InventorRoger Clarke
Life of this patent
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Abstract
A test verification circuit is described herein for verifying proper operation of a tested circuit, such as a voltage hazard warning circuit, using an N-channel MOSFET configured for switching ON and OFF the test verification circuit during a power outage, and a voltage source that provides an input voltage to the N-channel MOSFET from a conserved power supply. The N-channel MOSFET provides temporary power from a conserved power supply to the test verification circuit upon activation by a user during a power outage, and the test verification circuit determines whether the tested circuit has been de-energized, remains energized, or there remains inadequate power to complete the test.
Claims19
An ultra-low leakage test verification circuit for verifying proper operation of a tested circuit, comprising:
- an N-channel MOSFET configured for switching ON and OFF the test verification circuit during a power outage;
- and
- a voltage source that provides an input voltage to the N-channel MOSFET from a conserved power supply, wherein a potential at a gate of the N-channel MOSFET is biased to a level greater than an operational voltage of the test verification circuit;
- wherein the N-channel MOSFET provides temporary power from the conserved power supply to the test verification circuit upon activation by a user during a power outage;
- and
- wherein the test verification circuit determines whether the tested circuit has been de-energized, remains energized, or there remains inadequate power to complete the test.
A system that facilitates verifying operation of a tested circuit during a power outage, comprising:
- an ultra-low leakage test verification circuit for verifying proper operation of a shock hazard warning circuit;
- an N-channel MOSFET configured for switching ON and OFF the test verification circuit during said power outage;
- a voltage source that provides an input voltage to the N-channel MOSFET;
- and
- a tested shock hazard warning circuit that is diagnosed by the test verification circuit upon activation of the test verification circuit by a user during said power outage;
- wherein the N-channel MOSFET includes a gate biased to a potential level greater than an operational voltage of the test verification circuit and the N-channel MOSFET provides temporary power from a conserved power supply to the test verification circuit upon activation by the user;
- and
- wherein the test verification circuit verifies whether the tested circuit has been de-energized.
Dependencies are inferred from the claim text.