Method and apparatus for minimizing parasitic resistance of output capacitor in LDC

Abstract

A low-voltage DC-DC converter (LDC) includes: an N-phase power circuit configured by connection of N DC-DC converters in parallel between a high-voltage (HV) battery and a low-voltage (LV) battery; and one output capacitor commonly connected to an output of each phase DC-DC converter. Each phase of the N-phase power circuit is controlled in an interleaving manner which delays a phase by 360°/N. Here, each N-phase power circuit is controlled by switching at a frequency of [(a frequency at which the parasitic resistance (equivalent series resistance (ESR)) of the output capacitor is minimized)/N]. The parasitic resistance of the output capacitor of the LDC can be minimized. Accordingly, a lifespan of a battery can be improved and efficiency of the DC-DC converter can be increased through the reduction of the equivalent series resistance (ESR) of the output capacitor.

Dependencies are inferred from the claim text.