Back to results
US 11,882,684 B2Granted
Memory device comprising an electrically floating body transistor
AssigneeZeno Semiconductor, Inc.
InventorsYuniarto Widjaja, Jin-Woo Han
Life of this patent
Estimating the term…
Abstract
A semiconductor memory cell having an electrically floating body having two stable states is disclosed. A method of operating the memory cell is disclosed.
Claims16
A semiconductor memory array comprising a plurality of semiconductor memory cells arranged in a matrix of rows and columns, wherein at least two of said semiconductor memory cells each include:
- a floating body region configured to be charged to a level indicative of a state of the memory cell selected from at least first and second states;
- a first region in electrical contact with said floating body region;
- a second region in electrical contact with said floating body region and spaced apart from said first region;
- a gate positioned between said first and second regions;
- a first insulating region located above said floating body region;
- second insulating regions adjacent to said floating body region on opposite sides of said floating body region;
- and
- a well region adjacent to said floating body region and having a different conductivity type from a conductivity type of said floating body region, wherein:
- said floating body region is bounded by said first insulating region above said floating body region, said second insulating regions adjacent to said floating body region, said well region, and a depletion region formed as a result of an application of a back bias to said semiconductor memory cell;
- wherein said well region bounds at least two sides of said floating body region.
7 more elements
An integrated circuit comprising:
- a semiconductor memory array comprising a plurality of semiconductor memory cells arranged in a matrix of rows and columns, wherein at least two of said semiconductor memory cells each include:
- a floating body region configured to be charged to a level indicative of a state of the memory cell selected from at least first and second states;
- a first region in electrical contact with said floating body region;
- a second region in electrical contact with said floating body region and spaced apart from said first region;
- a gate positioned between said first and second regions;
- a first insulating region located above said floating body region;
- second insulating regions adjacent to said floating body region on opposite sides of said floating body region;
- and
- a well region adjacent to said floating body region and having a different conductivity type from a conductivity type of said floating body region, wherein:
- said floating body region is bounded by said first insulating region above said floating body region, said second insulating regions adjacent to said floating body region, said well region, and a depletion region formed as a result of an application of a back bias to said semiconductor memory cell;
- wherein said well region bounds at least two sides of said floating body region;
- and a control circuit to access said semiconductor memory cells.
9 more elements
Dependencies are inferred from the claim text.